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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_txstatem.v] - Diff between revs 236 and 276

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.5  2002/10/30 12:54:50  mohor
 
// State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.
 
//
// Revision 1.4  2002/01/23 10:28:16  mohor
// Revision 1.4  2002/01/23 10:28:16  mohor
// Link in the header changed.
// Link in the header changed.
//
//
// Revision 1.3  2001/10/19 08:43:51  mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// eth_timescale.v changed to timescale.v This is done because of the
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                      IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun,
                      IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun,
                      StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn,
                      StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn,
                      NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt,
                      NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt,
                      StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
                      StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
                      StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
                      StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
                      StartBackoff, StartDefer, StartPreamble, StartData, StartIPG
                      StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
                     );
                     );
 
 
parameter Tp = 1;
parameter Tp = 1;
 
 
input MTxClk;
input MTxClk;
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output StartFCS;          // FCS state will be activated in next clock
output StartFCS;          // FCS state will be activated in next clock
output StartJam;          // Jam state will be activated in next clock
output StartJam;          // Jam state will be activated in next clock
output StartBackoff;      // Backoff state will be activated in next clock
output StartBackoff;      // Backoff state will be activated in next clock
output StartDefer;        // Defer state will be activated in next clock
output StartDefer;        // Defer state will be activated in next clock
 
output DeferIndication;
output StartPreamble;     // Preamble state will be activated in next clock
output StartPreamble;     // Preamble state will be activated in next clock
output [1:0] StartData;   // Data state will be activated in next clock
output [1:0] StartData;   // Data state will be activated in next clock
output StartIPG;          // IPG state will be activated in next clock
output StartIPG;          // IPG state will be activated in next clock
 
 
wire StartIdle;           // Idle state will be activated in next clock
wire StartIdle;           // Idle state will be activated in next clock
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                  | StateIdle & CarrierSense
                  | StateIdle & CarrierSense
                  | StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax)
                  | StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax)
                  | StateBackOff & (TxUnderRun | RandomEqByteCnt)
                  | StateBackOff & (TxUnderRun | RandomEqByteCnt)
                  | StartTxDone | TooBig;
                  | StartTxDone | TooBig;
 
 
 
assign DeferIndication = StateIdle & CarrierSense;
 
 
// Tx State Machine
// Tx State Machine
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)

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