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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_txstatem.v] - Diff between revs 346 and 352

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Rev 346 Rev 352
Line 94... Line 94...
                      StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
                      StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
                      StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
                      StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
                      StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
                      StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
                     );
                     );
 
 
parameter Tp = 1;
 
 
 
input MTxClk;
input MTxClk;
input Reset;
input Reset;
input ExcessiveDefer;
input ExcessiveDefer;
input CarrierSense;
input CarrierSense;
input [6:0] NibCnt;
input [6:0] NibCnt;
Line 195... Line 193...
// Tx State Machine
// Tx State Machine
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    begin
    begin
      StateIPG        <= #Tp 1'b0;
      StateIPG        <=  1'b0;
      StateIdle       <= #Tp 1'b0;
      StateIdle       <=  1'b0;
      StatePreamble   <= #Tp 1'b0;
      StatePreamble   <=  1'b0;
      StateData[1:0]  <= #Tp 2'b0;
      StateData[1:0]  <=  2'b0;
      StatePAD        <= #Tp 1'b0;
      StatePAD        <=  1'b0;
      StateFCS        <= #Tp 1'b0;
      StateFCS        <=  1'b0;
      StateJam        <= #Tp 1'b0;
      StateJam        <=  1'b0;
      StateJam_q      <= #Tp 1'b0;
      StateJam_q      <=  1'b0;
      StateBackOff    <= #Tp 1'b0;
      StateBackOff    <=  1'b0;
      StateDefer      <= #Tp 1'b1;
      StateDefer      <=  1'b1;
    end
    end
  else
  else
    begin
    begin
      StateData[1:0] <= #Tp StartData[1:0];
      StateData[1:0] <=  StartData[1:0];
      StateJam_q <= #Tp StateJam;
      StateJam_q <=  StateJam;
 
 
      if(StartDefer | StartIdle)
      if(StartDefer | StartIdle)
        StateIPG <= #Tp 1'b0;
        StateIPG <=  1'b0;
      else
      else
      if(StartIPG)
      if(StartIPG)
        StateIPG <= #Tp 1'b1;
        StateIPG <=  1'b1;
 
 
      if(StartDefer | StartPreamble)
      if(StartDefer | StartPreamble)
        StateIdle <= #Tp 1'b0;
        StateIdle <=  1'b0;
      else
      else
      if(StartIdle)
      if(StartIdle)
        StateIdle <= #Tp 1'b1;
        StateIdle <=  1'b1;
 
 
      if(StartData[0] | StartJam)
      if(StartData[0] | StartJam)
        StatePreamble <= #Tp 1'b0;
        StatePreamble <=  1'b0;
      else
      else
      if(StartPreamble)
      if(StartPreamble)
        StatePreamble <= #Tp 1'b1;
        StatePreamble <=  1'b1;
 
 
      if(StartFCS | StartJam)
      if(StartFCS | StartJam)
        StatePAD <= #Tp 1'b0;
        StatePAD <=  1'b0;
      else
      else
      if(StartPAD)
      if(StartPAD)
        StatePAD <= #Tp 1'b1;
        StatePAD <=  1'b1;
 
 
      if(StartJam | StartDefer)
      if(StartJam | StartDefer)
        StateFCS <= #Tp 1'b0;
        StateFCS <=  1'b0;
      else
      else
      if(StartFCS)
      if(StartFCS)
        StateFCS <= #Tp 1'b1;
        StateFCS <=  1'b1;
 
 
      if(StartBackoff | StartDefer)
      if(StartBackoff | StartDefer)
        StateJam <= #Tp 1'b0;
        StateJam <=  1'b0;
      else
      else
      if(StartJam)
      if(StartJam)
        StateJam <= #Tp 1'b1;
        StateJam <=  1'b1;
 
 
      if(StartDefer)
      if(StartDefer)
        StateBackOff <= #Tp 1'b0;
        StateBackOff <=  1'b0;
      else
      else
      if(StartBackoff)
      if(StartBackoff)
        StateBackOff <= #Tp 1'b1;
        StateBackOff <=  1'b1;
 
 
      if(StartIPG)
      if(StartIPG)
        StateDefer <= #Tp 1'b0;
        StateDefer <=  1'b0;
      else
      else
      if(StartDefer)
      if(StartDefer)
        StateDefer <= #Tp 1'b1;
        StateDefer <=  1'b1;
    end
    end
end
end
 
 
 
 
// This sections defines which interpack gap rule to use
// This sections defines which interpack gap rule to use
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    Rule1 <= #Tp 1'b0;
    Rule1 <=  1'b0;
  else
  else
    begin
    begin
      if(StateIdle | StateBackOff)
      if(StateIdle | StateBackOff)
        Rule1 <= #Tp 1'b0;
        Rule1 <=  1'b0;
      else
      else
      if(StatePreamble | FullD)
      if(StatePreamble | FullD)
        Rule1 <= #Tp 1'b1;
        Rule1 <=  1'b1;
    end
    end
end
end
 
 
 
 
 
 

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