| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.21 2002/03/29 16:18:11 lampret
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// Small typo fixed.
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//
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// Revision 1.20 2002/03/25 16:19:12 mohor
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// Revision 1.20 2002/03/25 16:19:12 mohor
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// Any address can be used for Tx and Rx BD pointers. Address does not need
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// Any address can be used for Tx and Rx BD pointers. Address does not need
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// to be aligned.
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// to be aligned.
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//
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//
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// Revision 1.19 2002/03/19 12:51:50 mohor
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// Revision 1.19 2002/03/19 12:51:50 mohor
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| Line 278... |
Line 281... |
reg TxDone_wb;
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reg TxDone_wb;
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|
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reg TxDone_wb_q;
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reg TxDone_wb_q;
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reg TxAbort_wb_q;
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reg TxAbort_wb_q;
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reg TxRetry_wb_q;
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reg TxRetry_wb_q;
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reg TxDone_wb_q2;
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reg TxAbort_wb_q2;
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reg TxRetry_wb_q2;
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reg RxBDReady;
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reg RxBDReady;
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reg TxBDReady;
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reg TxBDReady;
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reg RxBDRead;
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reg RxBDRead;
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wire RxStatusWrite;
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wire RxStatusWrite;
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| Line 332... |
Line 338... |
reg TxEndFrm_wb;
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reg TxEndFrm_wb;
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wire TxRetryPulse;
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wire TxRetryPulse;
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wire TxDonePulse;
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wire TxDonePulse;
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wire TxAbortPulse;
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wire TxAbortPulse;
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wire TxRetryPulse_q;
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wire TxDonePulse_q;
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wire TxAbortPulse_q;
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wire StartRxBDRead;
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wire StartRxBDRead;
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wire StartTxBDRead;
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wire StartTxBDRead;
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| Line 767... |
Line 776... |
reg [3:0] m_wb_sel_tmp_rx;
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reg [3:0] m_wb_sel_tmp_rx;
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assign m_wb_sel_tmp_tx[0] = TxWordAcc | TxHalfAcc | TxByteAcc & TxPointer[1];
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assign m_wb_sel_tmp_tx[0] = TxWordAcc | TxHalfAcc | TxByteAcc & TxPointer[1];
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assign m_wb_sel_tmp_tx[1] = TxWordAcc | TxHalfAcc;
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assign m_wb_sel_tmp_tx[1] = TxWordAcc | TxHalfAcc;
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assign m_wb_sel_tmp_tx[2] = TxWordAcc | | TxByteAcc & ~TxPointer[1];
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assign m_wb_sel_tmp_tx[2] = TxWordAcc | TxByteAcc & ~TxPointer[1];
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assign m_wb_sel_tmp_tx[3] = TxWordAcc;
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assign m_wb_sel_tmp_tx[3] = TxWordAcc;
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wire MasterAccessFinished;
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wire MasterAccessFinished;
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| Line 796... |
Line 805... |
wire ResetReadTxDataFromMemory;
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wire ResetReadTxDataFromMemory;
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wire SetReadTxDataFromMemory;
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wire SetReadTxDataFromMemory;
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reg BlockReadTxDataFromMemory;
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reg BlockReadTxDataFromMemory;
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assign ResetReadTxDataFromMemory = (TxLengthEq0) | TxAbortPulse | TxRetryPulse;
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assign ResetReadTxDataFromMemory = (TxLengthEq0) | TxAbortPulse_q | TxRetryPulse_q;
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assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
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assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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| Line 849... |
Line 858... |
m_wb_sel_o <=#Tp 4'h0;
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m_wb_sel_o <=#Tp 4'h0;
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end
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end
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else
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else
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begin
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begin
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// Switching between two stages depends on enable signals
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// Switching between two stages depends on enable signals
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case ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished})
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case ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished}) // synopsys parallel_case
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5'b00_01_0, 5'b00_11_0 :
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5'b00_01_0, 5'b00_11_0 :
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begin
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begin
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MasterWbTX <=#Tp 1'b0; // idle and master write is needed (data write to rx buffer)
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MasterWbTX <=#Tp 1'b0; // idle and master write is needed (data write to rx buffer)
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MasterWbRX <=#Tp 1'b1;
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MasterWbRX <=#Tp 1'b1;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_adr_o <=#Tp RxPointer;
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| Line 951... |
Line 960... |
tx_fifo ( .data_in(tx_fifo_dat_i), .data_out(TxData_wb),
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tx_fifo ( .data_in(tx_fifo_dat_i), .data_out(TxData_wb),
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.clk(WB_CLK_I), .reset(Reset),
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.clk(WB_CLK_I), .reset(Reset),
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.write(MasterWbTX & m_wb_ack_i & m_wb_sel_o[0]), .read(ReadTxDataFromFifo_wb),
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.write(MasterWbTX & m_wb_ack_i & m_wb_sel_o[0]), .read(ReadTxDataFromFifo_wb),
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.clear(TxFifoClear), .full(TxBufferFull),
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.clear(TxFifoClear), .full(TxBufferFull),
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.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
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.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
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.empty(TxBufferEmpty)
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.empty(TxBufferEmpty), .cnt()
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);
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);
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|
|
|
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reg StartOccured;
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reg StartOccured;
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reg TxStartFrm_sync1;
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reg TxStartFrm_sync1;
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| Line 1140... |
Line 1149... |
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// Signals used for various purposes
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// Signals used for various purposes
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assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
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assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
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assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
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assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
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assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
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assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
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assign TxRetryPulse_q = TxRetry_wb_q & ~TxRetry_wb_q2;
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assign TxDonePulse_q = TxDone_wb_q & ~TxDone_wb_q2;
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assign TxAbortPulse_q = TxAbort_wb_q & ~TxAbort_wb_q2;
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|
|
|
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assign TPauseRq = 0;
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assign TPauseRq = 0;
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assign TxPauseTV[15:0] = TxLength[15:0];
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assign TxPauseTV[15:0] = TxLength[15:0];
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|
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| Line 1171... |
Line 1183... |
if(Reset)
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if(Reset)
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begin
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begin
|
TxDone_wb_q <=#Tp 1'b0;
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TxDone_wb_q <=#Tp 1'b0;
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TxAbort_wb_q <=#Tp 1'b0;
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TxAbort_wb_q <=#Tp 1'b0;
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TxRetry_wb_q <=#Tp 1'b0;
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TxRetry_wb_q <=#Tp 1'b0;
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TxDone_wb_q2 <=#Tp 1'b0;
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TxAbort_wb_q2 <=#Tp 1'b0;
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TxRetry_wb_q2 <=#Tp 1'b0;
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end
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end
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else
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else
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begin
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begin
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TxDone_wb_q <=#Tp TxDone_wb;
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TxDone_wb_q <=#Tp TxDone_wb;
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TxAbort_wb_q <=#Tp TxAbort_wb;
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TxAbort_wb_q <=#Tp TxAbort_wb;
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TxRetry_wb_q <=#Tp TxRetry_wb;
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TxRetry_wb_q <=#Tp TxRetry_wb;
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TxDone_wb_q2 <=#Tp TxDone_wb_q;
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TxAbort_wb_q2 <=#Tp TxAbort_wb_q;
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TxRetry_wb_q2 <=#Tp TxRetry_wb_q;
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end
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end
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end
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end
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// Sinchronizing and evaluating tx data
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// Sinchronizing and evaluating tx data
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| Line 1215... |
Line 1233... |
if(Flop & TxEndFrm | TxAbort | TxRetry_q)
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if(Flop & TxEndFrm | TxAbort | TxRetry_q)
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TxEndFrm <=#Tp 1'b0;
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TxEndFrm <=#Tp 1'b0;
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else
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else
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if(Flop & LastWord)
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if(Flop & LastWord)
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begin
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begin
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case (TxValidBytesLatched)
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case (TxValidBytesLatched) // synopsys parallel_case
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1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
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1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
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2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
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2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
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3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
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3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
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0 : TxEndFrm <=#Tp TxByteCnt == 2'h3;
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0 : TxEndFrm <=#Tp TxByteCnt == 2'h3;
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default : TxEndFrm <=#Tp 1'b0;
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default : TxEndFrm <=#Tp 1'b0;
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| Line 1233... |
Line 1251... |
begin
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begin
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if(Reset)
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if(Reset)
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TxData <=#Tp 0;
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TxData <=#Tp 0;
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else
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else
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if(TxStartFrm_sync2 & ~TxStartFrm)
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if(TxStartFrm_sync2 & ~TxStartFrm)
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case(TxPointerLatched)
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case(TxPointerLatched) // synopsys parallel_case
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2'h0 : TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
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2'h0 : TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
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2'h1 : TxData <=#Tp TxData_wb[23:16]; // Big Endian Byte Ordering
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2'h1 : TxData <=#Tp TxData_wb[23:16]; // Big Endian Byte Ordering
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2'h2 : TxData <=#Tp TxData_wb[15:08]; // Big Endian Byte Ordering
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2'h2 : TxData <=#Tp TxData_wb[15:08]; // Big Endian Byte Ordering
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2'h3 : TxData <=#Tp TxData_wb[07:00]; // Big Endian Byte Ordering
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2'h3 : TxData <=#Tp TxData_wb[07:00]; // Big Endian Byte Ordering
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endcase
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endcase
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| Line 1245... |
Line 1263... |
if(TxStartFrm & TxUsedData & TxPointerLatched==2'h3)
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if(TxStartFrm & TxUsedData & TxPointerLatched==2'h3)
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TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
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TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
|
else
|
else
|
if(TxUsedData & Flop)
|
if(TxUsedData & Flop)
|
begin
|
begin
|
case(TxByteCnt)
|
case(TxByteCnt) // synopsys parallel_case
|
0 : TxData <=#Tp TxDataLatched[31:24]; // Big Endian Byte Ordering
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0 : TxData <=#Tp TxDataLatched[31:24]; // Big Endian Byte Ordering
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1 : TxData <=#Tp TxDataLatched[23:16];
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1 : TxData <=#Tp TxDataLatched[23:16];
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2 : TxData <=#Tp TxDataLatched[15:8];
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2 : TxData <=#Tp TxDataLatched[15:8];
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3 : TxData <=#Tp TxDataLatched[7:0];
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3 : TxData <=#Tp TxDataLatched[7:0];
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endcase
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endcase
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| Line 1304... |
Line 1322... |
else
|
else
|
if(TxAbort_q | TxRetry_q)
|
if(TxAbort_q | TxRetry_q)
|
TxByteCnt <=#Tp 2'h0;
|
TxByteCnt <=#Tp 2'h0;
|
else
|
else
|
if(TxStartFrm & ~TxUsedData)
|
if(TxStartFrm & ~TxUsedData)
|
case(TxPointerLatched)
|
case(TxPointerLatched) // synopsys parallel_case
|
2'h0 : TxByteCnt <=#Tp 2'h1;
|
2'h0 : TxByteCnt <=#Tp 2'h1;
|
2'h1 : TxByteCnt <=#Tp 2'h2;
|
2'h1 : TxByteCnt <=#Tp 2'h2;
|
2'h2 : TxByteCnt <=#Tp 2'h3;
|
2'h2 : TxByteCnt <=#Tp 2'h3;
|
2'h3 : TxByteCnt <=#Tp 2'h0;
|
2'h3 : TxByteCnt <=#Tp 2'h0;
|
endcase
|
endcase
|
| Line 1529... |
Line 1547... |
end
|
end
|
|
|
|
|
always @ (RxPointerLatched)
|
always @ (RxPointerLatched)
|
begin
|
begin
|
case(RxPointerLatched[1:0])
|
case(RxPointerLatched[1:0]) // synopsys parallel_case
|
2'h0 : m_wb_sel_tmp_rx[3:0] = 4'hf;
|
2'h0 : m_wb_sel_tmp_rx[3:0] = 4'hf;
|
2'h1 : m_wb_sel_tmp_rx[3:0] = 4'h7;
|
2'h1 : m_wb_sel_tmp_rx[3:0] = 4'h7;
|
2'h2 : m_wb_sel_tmp_rx[3:0] = 4'h3;
|
2'h2 : m_wb_sel_tmp_rx[3:0] = 4'h3;
|
2'h3 : m_wb_sel_tmp_rx[3:0] = 4'h1;
|
2'h3 : m_wb_sel_tmp_rx[3:0] = 4'h1;
|
endcase
|
endcase
|
| Line 1642... |
Line 1660... |
else
|
else
|
if(ShiftEnded_tck | RxAbort)
|
if(ShiftEnded_tck | RxAbort)
|
RxByteCnt <=#Tp 2'h0;
|
RxByteCnt <=#Tp 2'h0;
|
else
|
else
|
if(RxValid & RxStartFrm & RxBDReady)
|
if(RxValid & RxStartFrm & RxBDReady)
|
case(RxPointerLatched)
|
case(RxPointerLatched) // synopsys parallel_case
|
2'h0 : RxByteCnt <=#Tp 2'h1;
|
2'h0 : RxByteCnt <=#Tp 2'h1;
|
2'h1 : RxByteCnt <=#Tp 2'h2;
|
2'h1 : RxByteCnt <=#Tp 2'h2;
|
2'h2 : RxByteCnt <=#Tp 2'h3;
|
2'h2 : RxByteCnt <=#Tp 2'h3;
|
2'h3 : RxByteCnt <=#Tp 2'h0;
|
2'h3 : RxByteCnt <=#Tp 2'h0;
|
endcase
|
endcase
|
| Line 1661... |
Line 1679... |
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxValidBytes <=#Tp 2'h1;
|
RxValidBytes <=#Tp 2'h1;
|
else
|
else
|
if(RxValid & RxStartFrm)
|
if(RxValid & RxStartFrm)
|
case(RxPointerLatched)
|
case(RxPointerLatched) // synopsys parallel_case
|
2'h0 : RxValidBytes <=#Tp 2'h1;
|
2'h0 : RxValidBytes <=#Tp 2'h1;
|
2'h1 : RxValidBytes <=#Tp 2'h2;
|
2'h1 : RxValidBytes <=#Tp 2'h2;
|
2'h2 : RxValidBytes <=#Tp 2'h3;
|
2'h2 : RxValidBytes <=#Tp 2'h3;
|
2'h3 : RxValidBytes <=#Tp 2'h0;
|
2'h3 : RxValidBytes <=#Tp 2'h0;
|
endcase
|
endcase
|
| Line 1711... |
Line 1729... |
else
|
else
|
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
|
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
|
RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
else
|
else
|
if(SetWriteRxDataToFifo & ShiftWillEnd)
|
if(SetWriteRxDataToFifo & ShiftWillEnd)
|
case(RxValidBytes)
|
case(RxValidBytes) // synopsys parallel_case
|
// 0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
// 0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
// 1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
|
// 1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
|
// 2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
|
// 2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
|
// 3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0};
|
// 3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0};
|
0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
| Line 1821... |
Line 1839... |
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
|
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
|
.clk(WB_CLK_I), .reset(Reset),
|
.clk(WB_CLK_I), .reset(Reset),
|
.write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i),
|
.write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i),
|
.clear(RxFifoReset), .full(RxBufferFull),
|
.clear(RxFifoReset), .full(RxBufferFull),
|
.almost_full(RxBufferAlmostFull), .almost_empty(RxBufferAlmostEmpty),
|
.almost_full(RxBufferAlmostFull), .almost_empty(RxBufferAlmostEmpty),
|
.empty(RxBufferEmpty)
|
.empty(RxBufferEmpty), .cnt()
|
);
|
);
|
|
|
assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty);
|
assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty);
|
|
|
|
|
