| Line 11... |
Line 11... |
//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.28 2002/07/18 16:11:46 mohor
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// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
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//
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// Revision 1.27 2002/07/11 02:53:20 mohor
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// Revision 1.27 2002/07/11 02:53:20 mohor
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// RxPointer bug fixed.
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// RxPointer bug fixed.
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//
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//
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// Revision 1.26 2002/07/10 13:12:38 mohor
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// Revision 1.26 2002/07/10 13:12:38 mohor
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// Previous bug wasn't succesfully removed. Now fixed.
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// Previous bug wasn't succesfully removed. Now fixed.
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| Line 1626... |
Line 1629... |
end
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end
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reg ShiftEnded_tck;
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reg ShiftEnded_tck;
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reg ShiftEndedSync1;
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reg ShiftEndedSync1;
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reg ShiftEndedSync2;
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reg ShiftEndedSync2;
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reg ShiftEndedSync3;
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reg ShiftEndedSync_c1;
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reg ShiftEndedSync_c2;
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wire StartShiftWillEnd;
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wire StartShiftWillEnd;
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//assign StartShiftWillEnd = LastByteIn & (&RxByteCnt) | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
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//assign StartShiftWillEnd = LastByteIn & (&RxByteCnt) | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
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assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
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assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
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// Indicating that data reception will end
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// Indicating that data reception will end
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| Line 1833... |
Line 1840... |
eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
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eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
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rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
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rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
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.clk(WB_CLK_I), .reset(Reset),
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.clk(WB_CLK_I), .reset(Reset),
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.write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i),
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.write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i),
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.clear(RxFifoReset), .full(RxBufferFull),
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.clear(RxFifoReset), .full(RxBufferFull),
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.almost_full(RxBufferAlmostFull), .almost_empty(RxBufferAlmostEmpty),
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.almost_full(), .almost_empty(RxBufferAlmostEmpty),
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.empty(RxBufferEmpty), .cnt()
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.empty(RxBufferEmpty), .cnt()
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);
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);
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assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty);
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assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty);
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| Line 1847... |
Line 1854... |
always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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ShiftEnded_tck <=#Tp 1'b0;
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ShiftEnded_tck <=#Tp 1'b0;
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else
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else
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if(SetWriteRxDataToFifo & StartShiftWillEnd & ~RxAbort & ~ShiftEnded_tck)
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if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
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ShiftEnded_tck <=#Tp 1'b1;
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ShiftEnded_tck <=#Tp 1'b1;
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else
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else
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if(ShiftEnded | RxAbort)
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if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
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ShiftEnded_tck <=#Tp 1'b0;
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ShiftEnded_tck <=#Tp 1'b0;
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end
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end
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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| Line 1870... |
Line 1877... |
ShiftEndedSync2 <=#Tp 1'b0;
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ShiftEndedSync2 <=#Tp 1'b0;
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else
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else
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ShiftEndedSync2 <=#Tp ShiftEndedSync1;
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ShiftEndedSync2 <=#Tp ShiftEndedSync1;
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end
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end
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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ShiftEndedSync3 <=#Tp 1'b0;
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else
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if(ShiftEndedSync1 & ~ShiftEndedSync2)
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ShiftEndedSync3 <=#Tp 1'b1;
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else
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if(ShiftEnded)
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ShiftEndedSync3 <=#Tp 1'b0;
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end
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// Generation of the end-of-frame signal
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// Generation of the end-of-frame signal
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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ShiftEnded <=#Tp 1'b0;
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ShiftEnded <=#Tp 1'b0;
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else
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else
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if(ShiftEndedSync2 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
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if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
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ShiftEnded <=#Tp 1'b1;
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ShiftEnded <=#Tp 1'b1;
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else
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else
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if(RxStatusWrite)
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if(RxStatusWrite)
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ShiftEnded <=#Tp 1'b0;
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ShiftEnded <=#Tp 1'b0;
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end
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end
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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ShiftEndedSync_c1 <=#Tp 1'b0;
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else
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ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
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end
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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ShiftEndedSync_c2 <=#Tp 1'b0;
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else
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ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
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end
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// Generation of the end-of-frame signal
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// Generation of the end-of-frame signal
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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