| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.30 2002/07/23 15:28:31 mohor
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// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
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//
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// Revision 1.29 2002/07/20 00:41:32 mohor
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// Revision 1.29 2002/07/20 00:41:32 mohor
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// ShiftEnded synchronization changed.
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// ShiftEnded synchronization changed.
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//
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//
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// Revision 1.28 2002/07/18 16:11:46 mohor
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// Revision 1.28 2002/07/18 16:11:46 mohor
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// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
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// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
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| Line 932... |
Line 935... |
MasterWbTX <=#Tp 1'b0; // whatever and no master read or write is needed (ack or err comes finishing previous access)
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MasterWbTX <=#Tp 1'b0; // whatever and no master read or write is needed (ack or err comes finishing previous access)
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MasterWbRX <=#Tp 1'b0;
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MasterWbRX <=#Tp 1'b0;
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m_wb_cyc_o <=#Tp 1'b0;
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m_wb_cyc_o <=#Tp 1'b0;
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m_wb_stb_o <=#Tp 1'b0;
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m_wb_stb_o <=#Tp 1'b0;
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end
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end
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6'b10_00_0_1, 6'b01_00_0_1 :
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begin
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MasterWbTX <=#Tp 1'b0; // Between cyc_cleared request was cleared
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MasterWbRX <=#Tp 1'b0;
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m_wb_cyc_o <=#Tp 1'b0;
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m_wb_stb_o <=#Tp 1'b0;
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end
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default: // Don't touch
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default: // Don't touch
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begin
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begin
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MasterWbTX <=#Tp MasterWbTX;
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MasterWbTX <=#Tp MasterWbTX;
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MasterWbRX <=#Tp MasterWbRX;
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MasterWbRX <=#Tp MasterWbRX;
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m_wb_cyc_o <=#Tp m_wb_cyc_o;
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m_wb_cyc_o <=#Tp m_wb_cyc_o;
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| Line 1847... |
Line 1857... |
.clear(RxFifoReset), .full(RxBufferFull),
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.clear(RxFifoReset), .full(RxBufferFull),
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.almost_full(), .almost_empty(RxBufferAlmostEmpty),
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.almost_full(), .almost_empty(RxBufferAlmostEmpty),
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.empty(RxBufferEmpty), .cnt()
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.empty(RxBufferEmpty), .cnt()
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);
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);
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assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty);
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assign WriteRxDataToMemory = ~RxBufferEmpty & ~MasterWbRX;
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// Generation of the end-of-frame signal
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// Generation of the end-of-frame signal
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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