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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 167 and 210

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Rev 167 Rev 210
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.37  2002/09/11 14:18:46  mohor
 
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
 
//
// Revision 1.36  2002/09/10 13:48:46  mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
// Reception is possible after RxPointer is read and not after BD is read. For
// Reception is possible after RxPointer is read and not after BD is read. For
// that reason RxBDReady is changed to RxReady.
// that reason RxBDReady is changed to RxReady.
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
// comes, interrupt is generated.
// comes, interrupt is generated.
Line 210... Line 213...
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
 
 
    // Tx Status
    // Tx Status
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
 
 
 
    // Bist
 
`ifdef ETH_BIST
 
   , trst, SO, SI, shift_DR, capture_DR, extest, tck
 
`endif
 
 
 
 
 
 
                );
                );
 
 
 
 
parameter Tp = 1;
parameter Tp = 1;
 
 
Line 293... Line 303...
output RxB_IRQ;
output RxB_IRQ;
output RxE_IRQ;
output RxE_IRQ;
output Busy_IRQ;
output Busy_IRQ;
 
 
 
 
 
// Bist
 
`ifdef ETH_BIST
 
input           trst;
 
input           shift_DR, capture_DR, tck, extest;
 
input           SI;
 
output          SO;
 
`endif
 
 
reg TxB_IRQ;
reg TxB_IRQ;
reg TxE_IRQ;
reg TxE_IRQ;
reg RxB_IRQ;
reg RxB_IRQ;
reg RxE_IRQ;
reg RxE_IRQ;
 
 
Line 438... Line 456...
assign WB_DAT_O = ram_do;
assign WB_DAT_O = ram_do;
 
 
// Generic synchronous single-port RAM interface
// Generic synchronous single-port RAM interface
eth_spram_256x32 bd_ram (
eth_spram_256x32 bd_ram (
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
 
`ifdef ETH_BIST
 
  , .trst(trst), .SO(SO), .SI(SI), .shift_DR(.shift_DR), .capture_DR(capture_DR), .extest(extest), .tck(tck)
 
`endif
);
);
 
 
assign ram_ce = 1'b1;
assign ram_ce = 1'b1;
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);

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