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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 210 and 219

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Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.38  2002/10/10 16:29:30  mohor
 
// BIST added.
 
//
// Revision 1.37  2002/09/11 14:18:46  mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
//
//
// Revision 1.36  2002/09/10 13:48:46  mohor
// Revision 1.36  2002/09/10 13:48:46  mohor
// Reception is possible after RxPointer is read and not after BD is read. For
// Reception is possible after RxPointer is read and not after BD is read. For
Line 192... Line 195...
    // WISHBONE master
    // WISHBONE master
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
 
 
 
`ifdef ETH_WISHBONE_B3
 
    m_wb_cti_o, m_wb_bte_o,
 
`endif
 
 
    //TX
    //TX
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
    PerPacketPad,
    PerPacketPad,
 
 
Line 248... Line 255...
output          m_wb_stb_o;     // 
output          m_wb_stb_o;     // 
input   [31:0]  m_wb_dat_i;     // 
input   [31:0]  m_wb_dat_i;     // 
input           m_wb_ack_i;     // 
input           m_wb_ack_i;     // 
input           m_wb_err_i;     // 
input           m_wb_err_i;     // 
 
 
 
`ifdef ETH_WISHBONE_B3
 
output   [2:0]  m_wb_cti_o;     // Cycle Type Identifier
 
output   [1:0]  m_wb_bte_o;     // Burst Type Extension
 
reg      [2:0]  m_wb_cti_o;     // Cycle Type Identifier
 
`endif
 
 
input           Reset;       // Reset signal
input           Reset;       // Reset signal
 
 
// Rx Status signals
// Rx Status signals
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
input           LatchedCrcError;  // CRC error
input           LatchedCrcError;  // CRC error
Line 342... Line 355...
reg             TxDone_wb;
reg             TxDone_wb;
 
 
reg             TxDone_wb_q;
reg             TxDone_wb_q;
reg             TxAbort_wb_q;
reg             TxAbort_wb_q;
reg             TxRetry_wb_q;
reg             TxRetry_wb_q;
reg             TxDone_wb_q2;
reg             TxRetryPacket;
reg             TxAbort_wb_q2;
reg             TxDonePulse_q;
reg             TxRetry_wb_q2;
reg             TxAbortPacket;
reg             RxBDReady;
reg             RxBDReady;
reg             RxReady;
reg             RxReady;
reg             TxBDReady;
reg             TxBDReady;
 
 
reg             RxBDRead;
reg             RxBDRead;
Line 399... Line 412...
reg             TxEndFrm_wb;
reg             TxEndFrm_wb;
 
 
wire            TxRetryPulse;
wire            TxRetryPulse;
wire            TxDonePulse;
wire            TxDonePulse;
wire            TxAbortPulse;
wire            TxAbortPulse;
wire            TxRetryPulse_q;
 
wire            TxDonePulse_q;
 
wire            TxAbortPulse_q;
 
 
 
wire            StartRxBDRead;
wire            StartRxBDRead;
 
 
wire            StartTxBDRead;
wire            StartTxBDRead;
 
 
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reg RxEn_needed;
reg RxEn_needed;
 
 
wire StartRxPointerRead;
wire StartRxPointerRead;
reg RxPointerRead;
reg RxPointerRead;
 
 
 
`ifdef ETH_WISHBONE_B3
 
assign m_wb_bte_o = 2'b00;    // Linear burst
 
`endif
 
 
 
 
always @ (posedge WB_CLK_I)
always @ (posedge WB_CLK_I)
begin
begin
  WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
  WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
end
end
Line 457... Line 471...
 
 
// Generic synchronous single-port RAM interface
// Generic synchronous single-port RAM interface
eth_spram_256x32 bd_ram (
eth_spram_256x32 bd_ram (
  .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
  .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
`ifdef ETH_BIST
`ifdef ETH_BIST
  , .trst(trst), .SO(SO), .SI(SI), .shift_DR(.shift_DR), .capture_DR(capture_DR), .extest(extest), .tck(tck)
  , .trst(trst), .SO(SO), .SI(SI), .shift_DR(shift_DR), .capture_DR(capture_DR), .extest(extest), .tck(tck)
`endif
`endif
);
);
 
 
assign ram_ce = 1'b1;
assign ram_ce = 1'b1;
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
Line 845... Line 859...
 
 
wire TxBufferAlmostFull;
wire TxBufferAlmostFull;
wire TxBufferFull;
wire TxBufferFull;
wire TxBufferEmpty;
wire TxBufferEmpty;
wire TxBufferAlmostEmpty;
wire TxBufferAlmostEmpty;
wire ResetReadTxDataFromMemory;
 
wire SetReadTxDataFromMemory;
wire SetReadTxDataFromMemory;
 
 
reg BlockReadTxDataFromMemory;
reg BlockReadTxDataFromMemory;
 
 
assign ResetReadTxDataFromMemory = (TxLengthEq0) | TxAbortPulse_q | TxRetryPulse_q;
 
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
 
 
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    ReadTxDataFromMemory <=#Tp 1'b0;
    ReadTxDataFromMemory <=#Tp 1'b0;
  else
  else
  if(ResetReadTxDataFromMemory)
  if(TxLengthEq0 | TxAbortPacket | TxRetryPacket)
    ReadTxDataFromMemory <=#Tp 1'b0;
    ReadTxDataFromMemory <=#Tp 1'b0;
  else
  else
  if(SetReadTxDataFromMemory)
  if(SetReadTxDataFromMemory)
    ReadTxDataFromMemory <=#Tp 1'b1;
    ReadTxDataFromMemory <=#Tp 1'b1;
end
end
Line 874... Line 886...
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    BlockReadTxDataFromMemory <=#Tp 1'b0;
    BlockReadTxDataFromMemory <=#Tp 1'b0;
  else
  else
  if(ReadTxDataFromFifo_wb | ResetReadTxDataFromMemory)
 
    BlockReadTxDataFromMemory <=#Tp 1'b0;
 
  else
 
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX)
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX)
    BlockReadTxDataFromMemory <=#Tp 1'b1;
    BlockReadTxDataFromMemory <=#Tp 1'b1;
 
  else
 
  if(ReadTxDataFromFifo_wb | TxDonePulse_q | TxAbortPacket | TxRetryPacket)
 
    BlockReadTxDataFromMemory <=#Tp 1'b0;
end
end
 
 
 
 
 
 
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
 
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
 
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
 
 
// Enabling master wishbone access to the memory for two devices TX and RX.
// Enabling master wishbone access to the memory for two devices TX and RX.
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
Line 1013... Line 1027...
end
end
 
 
 
 
wire TxFifoClear;
wire TxFifoClear;
 
 
assign TxFifoClear = (TxAbort_wb | TxRetry_wb) & ~TxBDReady;
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
wire [4:0] txfifo_cnt;
 
 
 
eth_fifo #(`TX_FIFO_DATA_WIDTH, `TX_FIFO_DEPTH, `TX_FIFO_CNT_WIDTH)
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
          .clk(WB_CLK_I),                                   .reset(Reset),
          .clk(WB_CLK_I),                                   .reset(Reset),
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb),
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
          .clear(TxFifoClear),                              .full(TxBufferFull),
          .clear(TxFifoClear),                              .full(TxBufferFull),
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
          .empty(TxBufferEmpty),                            .cnt(txfifo_cnt)
        );
        );
 
 
Line 1211... Line 1224...
 
 
// Signals used for various purposes
// Signals used for various purposes
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
assign TxRetryPulse_q = TxRetry_wb_q & ~TxRetry_wb_q2;
 
assign TxDonePulse_q  = TxDone_wb_q  & ~TxDone_wb_q2;
 
assign TxAbortPulse_q = TxAbort_wb_q & ~TxAbort_wb_q2;
 
 
 
 
 
 
 
// Generating delayed signals
// Generating delayed signals
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
Line 1242... Line 1252...
  if(Reset)
  if(Reset)
    begin
    begin
      TxDone_wb_q   <=#Tp 1'b0;
      TxDone_wb_q   <=#Tp 1'b0;
      TxAbort_wb_q  <=#Tp 1'b0;
      TxAbort_wb_q  <=#Tp 1'b0;
      TxRetry_wb_q  <=#Tp 1'b0;
      TxRetry_wb_q  <=#Tp 1'b0;
      TxDone_wb_q2  <=#Tp 1'b0;
      TxDonePulse_q  <=#Tp 1'b0;
      TxAbort_wb_q2 <=#Tp 1'b0;
 
      TxRetry_wb_q2 <=#Tp 1'b0;
 
    end
    end
  else
  else
    begin
    begin
      TxDone_wb_q   <=#Tp TxDone_wb;
      TxDone_wb_q   <=#Tp TxDone_wb;
      TxAbort_wb_q  <=#Tp TxAbort_wb;
      TxAbort_wb_q  <=#Tp TxAbort_wb;
      TxRetry_wb_q  <=#Tp TxRetry_wb;
      TxRetry_wb_q  <=#Tp TxRetry_wb;
      TxDone_wb_q2  <=#Tp TxDone_wb_q;
      TxDonePulse_q  <=#Tp TxDonePulse;
      TxAbort_wb_q2 <=#Tp TxAbort_wb_q;
 
      TxRetry_wb_q2 <=#Tp TxRetry_wb_q;
 
    end
    end
end
end
 
 
 
 
 
reg TxAbortPacketBlocked;
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
  if(Reset)
 
    TxAbortPacket <=#Tp 1'b0;
 
  else
 
  if(TxAbort_wb & (!TxAbortPacketBlocked) & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
 
    TxAbortPacket <=#Tp 1'b1;
 
  else
 
    TxAbortPacket <=#Tp 1'b0;
 
end
 
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
  if(Reset)
 
    TxAbortPacketBlocked <=#Tp 1'b0;
 
  else
 
  if(TxAbortPacket)
 
    TxAbortPacketBlocked <=#Tp 1'b1;
 
  else
 
  if(!TxAbort_wb & TxAbort_wb_q)
 
    TxAbortPacketBlocked <=#Tp 1'b0;
 
end
 
 
 
 
 
reg TxRetryPacketBlocked;
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
  if(Reset)
 
    TxRetryPacket <=#Tp 1'b0;
 
  else
 
  if(TxRetry_wb & (!TxRetryPacketBlocked) & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
 
    TxRetryPacket <=#Tp 1'b1;
 
  else
 
    TxRetryPacket <=#Tp 1'b0;
 
end
 
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
  if(Reset)
 
    TxRetryPacketBlocked <=#Tp 1'b0;
 
  else
 
  if(TxRetryPacket)
 
    TxRetryPacketBlocked <=#Tp 1'b1;
 
  else
 
  if(!TxRetry_wb & TxRetry_wb_q)
 
    TxRetryPacketBlocked <=#Tp 1'b0;
 
end
 
 
 
 
// Sinchronizing and evaluating tx data
// Sinchronizing and evaluating tx data
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
assign SetGotData = (TxStartFrm_wb); // igor namesto zgornje
assign SetGotData = (TxStartFrm_wb);
 
 
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
 
 
Line 1936... Line 1994...
end
end
 
 
 
 
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
 
 
wire [4:0] rxfifo_cnt;
 
 
 
eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
         .clk(WB_CLK_I),                                .reset(Reset),
         .clk(WB_CLK_I),                                .reset(Reset),
         .write(WriteRxDataToFifo_wb),                  .read(MasterWbRX & m_wb_ack_i),
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
         .clear(RxFifoReset),                           .full(RxBufferFull),
         .clear(RxFifoReset),                           .full(RxBufferFull),
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
        );
        );
 
 
assign WriteRxDataToMemory = ~RxBufferEmpty & ~MasterWbRX;
assign WriteRxDataToMemory = ~RxBufferEmpty;
 
 
 
 
 
 
// Generation of the end-of-frame signal
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
Line 2040... Line 2097...
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    RxAbortSync1 <=#Tp 1'b0;
    RxAbortSync1 <=#Tp 1'b0;
  else
  else
//    RxAbortSync1 <=#Tp RxAbort;
 
    RxAbortSync1 <=#Tp RxAbortLatched;
    RxAbortSync1 <=#Tp RxAbortLatched;
end
end
 
 
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin

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