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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 219 and 221

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Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.39  2002/10/11 15:35:20  mohor
 
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
 
// TxDone and TxRetry are generated after the current WISHBONE access is
 
// finished.
 
//
// Revision 1.38  2002/10/10 16:29:30  mohor
// Revision 1.38  2002/10/10 16:29:30  mohor
// BIST added.
// BIST added.
//
//
// Revision 1.37  2002/09/11 14:18:46  mohor
// Revision 1.37  2002/09/11 14:18:46  mohor
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
Line 356... Line 361...
 
 
reg             TxDone_wb_q;
reg             TxDone_wb_q;
reg             TxAbort_wb_q;
reg             TxAbort_wb_q;
reg             TxRetry_wb_q;
reg             TxRetry_wb_q;
reg             TxRetryPacket;
reg             TxRetryPacket;
reg             TxDonePulse_q;
reg             TxRetryPacket_NotCleared;
 
reg             TxDonePacket;
 
reg             TxDonePacket_NotCleared;
reg             TxAbortPacket;
reg             TxAbortPacket;
 
reg             TxAbortPacket_NotCleared;
reg             RxBDReady;
reg             RxBDReady;
reg             RxReady;
reg             RxReady;
reg             TxBDReady;
reg             TxBDReady;
 
 
reg             RxBDRead;
reg             RxBDRead;
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    TxBDReady <=#Tp 1'b0;
    TxBDReady <=#Tp 1'b0;
end
end
 
 
 
 
// Reading the Tx buffer descriptor
// Reading the Tx buffer descriptor
assign StartTxBDRead = (TxRetry_wb | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
 
 
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    TxBDRead <=#Tp 1'b1;
    TxBDRead <=#Tp 1'b1;
Line 653... Line 661...
    TxPointerRead <=#Tp 1'b0;
    TxPointerRead <=#Tp 1'b0;
end
end
 
 
 
 
// Writing status back to the Tx buffer descriptor
// Writing status back to the Tx buffer descriptor
assign TxStatusWrite = (TxDone_wb | TxAbort_wb) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
 
 
 
 
 
 
// Status writing must occur only once. Meanwhile it is blocked.
// Status writing must occur only once. Meanwhile it is blocked.
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
Line 877... Line 885...
  else
  else
  if(SetReadTxDataFromMemory)
  if(SetReadTxDataFromMemory)
    ReadTxDataFromMemory <=#Tp 1'b1;
    ReadTxDataFromMemory <=#Tp 1'b1;
end
end
 
 
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
reg BlockingLastReadOn_Abort_Retry;
 
 
 
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory & ~BlockingLastReadOn_Abort_Retry;
 
 
wire [31:0] TxData_wb;
wire [31:0] TxData_wb;
wire ReadTxDataFromFifo_wb;
wire ReadTxDataFromFifo_wb;
 
 
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    BlockReadTxDataFromMemory <=#Tp 1'b0;
    BlockReadTxDataFromMemory <=#Tp 1'b0;
  else
  else
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX)
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (!(TxAbortPacket | TxRetryPacket)))
    BlockReadTxDataFromMemory <=#Tp 1'b1;
    BlockReadTxDataFromMemory <=#Tp 1'b1;
  else
  else
  if(ReadTxDataFromFifo_wb | TxDonePulse_q | TxAbortPacket | TxRetryPacket)
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
    BlockReadTxDataFromMemory <=#Tp 1'b0;
    BlockReadTxDataFromMemory <=#Tp 1'b0;
end
end
 
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
  if(Reset)
 
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
 
  else
 
  if(TxAbortPacket | TxRetryPacket)
 
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b0;
 
  else
 
  if(((TxAbort_wb & !TxAbortPacket_NotCleared) | (TxRetry_wb & !TxRetryPacket_NotCleared)) & !TxBDReady)
 
    BlockingLastReadOn_Abort_Retry <=#Tp 1'b1;
 
end
 
 
 
 
 
 
 
 
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
 
 
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          begin
          begin
            MasterWbTX <=#Tp 1'b0;  // Between cyc_cleared request was cleared
            MasterWbTX <=#Tp 1'b0;  // Between cyc_cleared request was cleared
            MasterWbRX <=#Tp 1'b0;
            MasterWbRX <=#Tp 1'b0;
            m_wb_cyc_o <=#Tp 1'b0;
            m_wb_cyc_o <=#Tp 1'b0;
            m_wb_stb_o <=#Tp 1'b0;
            m_wb_stb_o <=#Tp 1'b0;
 
            cyc_cleared<=#Tp 1'b0;
            IncrTxPointer<=#Tp 1'b0;
            IncrTxPointer<=#Tp 1'b0;
          end
          end
        default:                            // Don't touch
        default:                            // Don't touch
          begin
          begin
            MasterWbTX <=#Tp MasterWbTX;
            MasterWbTX <=#Tp MasterWbTX;
Line 1126... Line 1152...
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    TxEndFrm_wb <=#Tp 1'b0;
    TxEndFrm_wb <=#Tp 1'b0;
  else
  else
  if(TxLengthLt4 & TxBufferAlmostEmpty & TxUsedData)
  if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
    TxEndFrm_wb <=#Tp 1'b1;
    TxEndFrm_wb <=#Tp 1'b1;
  else
  else
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
    TxEndFrm_wb <=#Tp 1'b0;
    TxEndFrm_wb <=#Tp 1'b0;
end
end
Line 1252... Line 1278...
  if(Reset)
  if(Reset)
    begin
    begin
      TxDone_wb_q   <=#Tp 1'b0;
      TxDone_wb_q   <=#Tp 1'b0;
      TxAbort_wb_q  <=#Tp 1'b0;
      TxAbort_wb_q  <=#Tp 1'b0;
      TxRetry_wb_q  <=#Tp 1'b0;
      TxRetry_wb_q  <=#Tp 1'b0;
      TxDonePulse_q  <=#Tp 1'b0;
 
    end
    end
  else
  else
    begin
    begin
      TxDone_wb_q   <=#Tp TxDone_wb;
      TxDone_wb_q   <=#Tp TxDone_wb;
      TxAbort_wb_q  <=#Tp TxAbort_wb;
      TxAbort_wb_q  <=#Tp TxAbort_wb;
      TxRetry_wb_q  <=#Tp TxRetry_wb;
      TxRetry_wb_q  <=#Tp TxRetry_wb;
      TxDonePulse_q  <=#Tp TxDonePulse;
 
    end
    end
end
end
 
 
 
 
reg TxAbortPacketBlocked;
reg TxAbortPacketBlocked;
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always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
 
    TxAbortPacket_NotCleared <=#Tp 1'b0;
 
  else
 
  if(TxAbort_wb & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
 
    TxAbortPacket_NotCleared <=#Tp 1'b1;
 
  else
 
    TxAbortPacket_NotCleared <=#Tp 1'b0;
 
end
 
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
  if(Reset)
    TxAbortPacketBlocked <=#Tp 1'b0;
    TxAbortPacketBlocked <=#Tp 1'b0;
  else
  else
  if(TxAbortPacket)
  if(TxAbortPacket)
    TxAbortPacketBlocked <=#Tp 1'b1;
    TxAbortPacketBlocked <=#Tp 1'b1;
  else
  else
Line 1306... Line 1342...
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
 
    TxRetryPacket_NotCleared <=#Tp 1'b0;
 
  else
 
  if(TxRetry_wb & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
 
    TxRetryPacket_NotCleared <=#Tp 1'b1;
 
  else
 
    TxRetryPacket_NotCleared <=#Tp 1'b0;
 
end
 
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
  if(Reset)
    TxRetryPacketBlocked <=#Tp 1'b0;
    TxRetryPacketBlocked <=#Tp 1'b0;
  else
  else
  if(TxRetryPacket)
  if(TxRetryPacket)
    TxRetryPacketBlocked <=#Tp 1'b1;
    TxRetryPacketBlocked <=#Tp 1'b1;
  else
  else
  if(!TxRetry_wb & TxRetry_wb_q)
  if(!TxRetry_wb & TxRetry_wb_q)
    TxRetryPacketBlocked <=#Tp 1'b0;
    TxRetryPacketBlocked <=#Tp 1'b0;
end
end
 
 
 
 
 
reg TxDonePacketBlocked;
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
  if(Reset)
 
    TxDonePacket <=#Tp 1'b0;
 
  else
 
  if(TxDone_wb & (!TxDonePacketBlocked) & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
 
    TxDonePacket <=#Tp 1'b1;
 
  else
 
    TxDonePacket <=#Tp 1'b0;
 
end
 
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
  if(Reset)
 
    TxDonePacket_NotCleared <=#Tp 1'b0;
 
  else
 
  if(TxDone_wb & (MasterWbTX & MasterAccessFinished | (!MasterWbTX)))
 
    TxDonePacket_NotCleared <=#Tp 1'b1;
 
  else
 
    TxDonePacket_NotCleared <=#Tp 1'b0;
 
end
 
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
  if(Reset)
 
    TxDonePacketBlocked <=#Tp 1'b0;
 
  else
 
  if(TxDonePacket)
 
    TxDonePacketBlocked <=#Tp 1'b1;
 
  else
 
  if(!TxDone_wb & TxDone_wb_q)
 
    TxDonePacketBlocked <=#Tp 1'b0;
 
end
 
 
 
 
// Sinchronizing and evaluating tx data
// Sinchronizing and evaluating tx data
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
assign SetGotData = (TxStartFrm_wb);
assign SetGotData = (TxStartFrm_wb);
 
 
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
Line 2007... Line 2093...
        );
        );
 
 
assign WriteRxDataToMemory = ~RxBufferEmpty;
assign WriteRxDataToMemory = ~RxBufferEmpty;
 
 
 
 
 
 
// Generation of the end-of-frame signal
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    ShiftEnded_rck <=#Tp 1'b0;
    ShiftEnded_rck <=#Tp 1'b0;

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