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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 239 and 250

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Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.44  2002/11/13 22:21:40  tadejm
 
// RxError is not generated when small frame reception is enabled and small
 
// frames are received.
 
//
// Revision 1.43  2002/10/18 20:53:34  mohor
// Revision 1.43  2002/10/18 20:53:34  mohor
// case changed to casex.
// case changed to casex.
//
//
// Revision 1.42  2002/10/18 17:04:20  tadejm
// Revision 1.42  2002/10/18 17:04:20  tadejm
// Changed BIST scan signals.
// Changed BIST scan signals.
Line 233... Line 237...
    // Interrupts
    // Interrupts
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
 
 
    // Rx Status
    // Rx Status
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
 
 
    // Tx Status
    // Tx Status
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
 
 
    // Bist
    // Bist
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input           DribbleNibble;    // Extra nibble received
input           DribbleNibble;    // Extra nibble received
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
input    [15:0] RxLength;         // Length of the incoming frame
input    [15:0] RxLength;         // Length of the incoming frame
input           LoadRxStatus;     // Rx status was loaded
input           LoadRxStatus;     // Rx status was loaded
input           ReceivedPacketGood;// Received packet's length and CRC are good
input           ReceivedPacketGood;// Received packet's length and CRC are good
 
input           AddressMiss;      // When a packet is received AddressMiss status is written to the Rx BD
 
 
// Tx Status signals
// Tx Status signals
input     [3:0] RetryCntLatched;  // Latched Retry Counter
input     [3:0] RetryCntLatched;  // Latched Retry Counter
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
input           LateCollLatched;  // Late collision occured
input           LateCollLatched;  // Late collision occured
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wire            SetGotData;
wire            SetGotData;
wire            GotDataEvaluate;
wire            GotDataEvaluate;
 
 
reg             WB_ACK_O;
reg             WB_ACK_O;
 
 
wire    [6:0]   RxStatusIn;
wire    [7:0]   RxStatusIn;
reg     [6:0]   RxStatusInLatched;
reg     [7:0]   RxStatusInLatched;
 
 
reg WbEn, WbEn_q;
reg WbEn, WbEn_q;
reg RxEn, RxEn_q;
reg RxEn, RxEn_q;
reg TxEn, TxEn_q;
reg TxEn, TxEn_q;
 
 
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    RxBDAddress <=#Tp TempRxBDAddress;
    RxBDAddress <=#Tp TempRxBDAddress;
end
end
 
 
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
 
 
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 6'h0, RxStatusInLatched};
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 5'h0, RxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
 
 
 
 
// Signals used for various purposes
// Signals used for various purposes
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
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  if(LoadRxStatus)
  if(LoadRxStatus)
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
end
end
 
 
 
 
assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
assign RxStatusIn = {AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
 
 
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    RxStatusInLatched <=#Tp 'h0;
    RxStatusInLatched <=#Tp 'h0;
Line 2391... Line 2396...
 
 
wire RxError;
wire RxError;
 
 
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
// are aborted when signal r_RecSmall is set to 0 in MODER register.
// are aborted when signal r_RecSmall is set to 0 in MODER register.
 
// AddressMiss is identifying that a frame was received because of the promiscous
 
// mode and is not an error
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
 
 
// Tx Done Interrupt
// Tx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin

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