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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 261 and 264

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Rev 261 Rev 264
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.46  2002/11/22 01:57:06  mohor
 
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
 
// synchronized.
 
//
// Revision 1.45  2002/11/19 17:33:34  mohor
// Revision 1.45  2002/11/19 17:33:34  mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
// that a frame was received because of the promiscous mode.
//
//
// Revision 1.44  2002/11/13 22:21:40  tadejm
// Revision 1.44  2002/11/13 22:21:40  tadejm
Line 1803... Line 1807...
reg RxAbortSync3;
reg RxAbortSync3;
reg RxAbortSync4;
reg RxAbortSync4;
reg RxAbortSyncb1;
reg RxAbortSyncb1;
reg RxAbortSyncb2;
reg RxAbortSyncb2;
 
 
//assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
 
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
 
 
// Reading the Rx buffer descriptor
// Reading the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
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// Reception status is written back to the buffer descriptor after the end of frame is detected.
// Reception status is written back to the buffer descriptor after the end of frame is detected.
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
 
 
reg RxStatusWriteLatched;
 
reg RxStatusWrite_rck;
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
  if(Reset)
 
    RxStatusWriteLatched <=#Tp 1'b0;
 
  else
 
  if(RxStatusWrite & ~RxStatusWrite_rck)
 
    RxStatusWriteLatched <=#Tp 1'b1;
 
  else
 
  if(RxStatusWrite_rck)
 
    RxStatusWriteLatched <=#Tp 1'b0;
 
end
 
 
 
 
 
always @ (posedge MRxClk or posedge Reset)
 
begin
 
  if(Reset)
 
    RxStatusWrite_rck <=#Tp 1'b0;
 
  else
 
  if(RxStatusWriteLatched)
 
    RxStatusWrite_rck <=#Tp 1'b1;
 
  else
 
    RxStatusWrite_rck <=#Tp 1'b0;
 
end
 
 
 
 
 
reg RxEnableWindow;
reg RxEnableWindow;
 
 
// Indicating that last byte is being reveived
// Indicating that last byte is being reveived
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin

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