| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.46 2002/11/22 01:57:06 mohor
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// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
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// synchronized.
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//
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// Revision 1.45 2002/11/19 17:33:34 mohor
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// Revision 1.45 2002/11/19 17:33:34 mohor
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// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
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// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
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// that a frame was received because of the promiscous mode.
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// that a frame was received because of the promiscous mode.
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//
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//
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// Revision 1.44 2002/11/13 22:21:40 tadejm
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// Revision 1.44 2002/11/13 22:21:40 tadejm
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| Line 1803... |
Line 1807... |
reg RxAbortSync3;
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reg RxAbortSync3;
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reg RxAbortSync4;
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reg RxAbortSync4;
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reg RxAbortSyncb1;
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reg RxAbortSyncb1;
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reg RxAbortSyncb2;
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reg RxAbortSyncb2;
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//assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
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assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
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assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4;
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// Reading the Rx buffer descriptor
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// Reading the Rx buffer descriptor
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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| Line 1936... |
Line 1939... |
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// Reception status is written back to the buffer descriptor after the end of frame is detected.
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// Reception status is written back to the buffer descriptor after the end of frame is detected.
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assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
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assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
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reg RxStatusWriteLatched;
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reg RxStatusWrite_rck;
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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RxStatusWriteLatched <=#Tp 1'b0;
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else
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if(RxStatusWrite & ~RxStatusWrite_rck)
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RxStatusWriteLatched <=#Tp 1'b1;
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else
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if(RxStatusWrite_rck)
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RxStatusWriteLatched <=#Tp 1'b0;
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end
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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RxStatusWrite_rck <=#Tp 1'b0;
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else
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if(RxStatusWriteLatched)
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RxStatusWrite_rck <=#Tp 1'b1;
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else
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RxStatusWrite_rck <=#Tp 1'b0;
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end
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reg RxEnableWindow;
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reg RxEnableWindow;
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// Indicating that last byte is being reveived
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// Indicating that last byte is being reveived
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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