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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 264 and 269

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Rev 264 Rev 269
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.47  2002/11/22 13:26:21  mohor
 
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
 
// anywhere. Removed.
 
//
// Revision 1.46  2002/11/22 01:57:06  mohor
// Revision 1.46  2002/11/22 01:57:06  mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
// synchronized.
//
//
// Revision 1.45  2002/11/19 17:33:34  mohor
// Revision 1.45  2002/11/19 17:33:34  mohor
Line 941... Line 945...
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    BlockReadTxDataFromMemory <=#Tp 1'b0;
    BlockReadTxDataFromMemory <=#Tp 1'b0;
  else
  else
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (!(TxAbortPacket | TxRetryPacket)))
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket | TxRetryPacket)))
    BlockReadTxDataFromMemory <=#Tp 1'b1;
    BlockReadTxDataFromMemory <=#Tp 1'b1;
  else
  else
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
  if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
    BlockReadTxDataFromMemory <=#Tp 1'b0;
    BlockReadTxDataFromMemory <=#Tp 1'b0;
end
end

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