| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.49 2003/01/21 12:09:40 mohor
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// When receiving normal data frame and RxFlow control was switched on, RXB
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// interrupt was not set.
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//
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// Revision 1.48 2003/01/20 12:05:26 mohor
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// Revision 1.48 2003/01/20 12:05:26 mohor
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// When in full duplex, transmit was sometimes blocked. Fixed.
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// When in full duplex, transmit was sometimes blocked. Fixed.
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//
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//
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// Revision 1.47 2002/11/22 13:26:21 mohor
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// Revision 1.47 2002/11/22 13:26:21 mohor
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// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
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// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
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| Line 242... |
Line 246... |
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
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MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
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TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
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TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
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PerPacketPad,
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PerPacketPad,
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//RX
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//RX
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MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
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MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
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// Register
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// Register
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r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow, r_PassAll,
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r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow, r_PassAll,
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// Interrupts
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// Interrupts
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| Line 349... |
Line 353... |
input [7:0] RxData; // Received data byte (from PHY)
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input [7:0] RxData; // Received data byte (from PHY)
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input RxValid; //
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input RxValid; //
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input RxStartFrm; //
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input RxStartFrm; //
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input RxEndFrm; //
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input RxEndFrm; //
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input RxAbort; // This signal is set when address doesn't match.
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input RxAbort; // This signal is set when address doesn't match.
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output RxStatusWriteLatched_sync2;
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//Register
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//Register
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input r_TxEn; // Transmit enable
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input r_TxEn; // Transmit enable
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input r_RxEn; // Receive enable
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input r_RxEn; // Receive enable
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input [7:0] r_TxBDNum; // Receive buffer descriptor number
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input [7:0] r_TxBDNum; // Receive buffer descriptor number
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| Line 415... |
Line 420... |
reg RxBDReady;
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reg RxBDReady;
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reg RxReady;
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reg RxReady;
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reg TxBDReady;
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reg TxBDReady;
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reg RxBDRead;
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reg RxBDRead;
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wire RxStatusWrite;
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reg [31:0] TxDataLatched;
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reg [31:0] TxDataLatched;
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reg [1:0] TxByteCnt;
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reg [1:0] TxByteCnt;
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reg LastWord;
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reg LastWord;
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reg ReadTxDataFromFifo_tck;
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reg ReadTxDataFromFifo_tck;
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| Line 483... |
Line 487... |
wire [7:0] TempRxBDAddress;
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wire [7:0] TempRxBDAddress;
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wire SetGotData;
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wire SetGotData;
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wire GotDataEvaluate;
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wire GotDataEvaluate;
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wire RxStatusWrite;
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reg WB_ACK_O;
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reg WB_ACK_O;
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wire [8:0] RxStatusIn;
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wire [8:0] RxStatusIn;
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reg [8:0] RxStatusInLatched;
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reg [8:0] RxStatusInLatched;
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| Line 720... |
Line 726... |
always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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BlockingTxStatusWrite <=#Tp 1'b0;
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BlockingTxStatusWrite <=#Tp 1'b0;
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else
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else
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if(TxStatusWrite)
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BlockingTxStatusWrite <=#Tp 1'b1;
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else
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if(~TxDone_wb & ~TxAbort_wb)
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if(~TxDone_wb & ~TxAbort_wb)
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BlockingTxStatusWrite <=#Tp 1'b0;
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BlockingTxStatusWrite <=#Tp 1'b0;
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else
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if(TxStatusWrite)
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BlockingTxStatusWrite <=#Tp 1'b1;
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end
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end
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reg BlockingTxStatusWrite_sync1;
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reg BlockingTxStatusWrite_sync1;
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reg BlockingTxStatusWrite_sync2;
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reg BlockingTxStatusWrite_sync2;
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| Line 1430... |
Line 1436... |
always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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TxAbortPacket_NotCleared <=#Tp 1'b0;
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TxAbortPacket_NotCleared <=#Tp 1'b0;
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else
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else
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if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
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TxAbortPacket_NotCleared <=#Tp 1'b0;
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else
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if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
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if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
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TxAbort_wb & !MasterWbTX)
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TxAbort_wb & !MasterWbTX)
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TxAbortPacket_NotCleared <=#Tp 1'b1;
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TxAbortPacket_NotCleared <=#Tp 1'b1;
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else
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TxAbortPacket_NotCleared <=#Tp 1'b0;
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end
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end
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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| Line 1470... |
Line 1477... |
always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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TxRetryPacket_NotCleared <=#Tp 1'b0;
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TxRetryPacket_NotCleared <=#Tp 1'b0;
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else
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else
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if(StartTxBDRead)
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TxRetryPacket_NotCleared <=#Tp 1'b0;
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else
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if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
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if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
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TxRetry_wb & !MasterWbTX)
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TxRetry_wb & !MasterWbTX)
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TxRetryPacket_NotCleared <=#Tp 1'b1;
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TxRetryPacket_NotCleared <=#Tp 1'b1;
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else
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TxRetryPacket_NotCleared <=#Tp 1'b0;
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end
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end
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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| Line 1510... |
Line 1518... |
always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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TxDonePacket_NotCleared <=#Tp 1'b0;
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TxDonePacket_NotCleared <=#Tp 1'b0;
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else
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else
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if(TxEn & TxEn_q & TxDonePacket_NotCleared)
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TxDonePacket_NotCleared <=#Tp 1'b0;
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else
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if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
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if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
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TxDone_wb & !MasterWbTX)
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TxDone_wb & !MasterWbTX)
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TxDonePacket_NotCleared <=#Tp 1'b1;
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TxDonePacket_NotCleared <=#Tp 1'b1;
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else
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TxDonePacket_NotCleared <=#Tp 1'b0;
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end
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end
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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| Line 2390... |
Line 2399... |
// are aborted when signal r_RecSmall is set to 0 in MODER register.
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// are aborted when signal r_RecSmall is set to 0 in MODER register.
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// AddressMiss is identifying that a frame was received because of the promiscous
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// AddressMiss is identifying that a frame was received because of the promiscous
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// mode and is not an error
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// mode and is not an error
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assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
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assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
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reg RxStatusWriteLatched;
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reg RxStatusWriteLatched_sync1;
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reg RxStatusWriteLatched_sync2;
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reg RxStatusWriteLatched_syncb1;
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reg RxStatusWriteLatched_syncb2;
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// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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RxStatusWriteLatched <=#Tp 1'b0;
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else
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if(RxStatusWriteLatched_syncb2)
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RxStatusWriteLatched <=#Tp 1'b0;
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else
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if(RxStatusWrite)
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RxStatusWriteLatched <=#Tp 1'b1;
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end
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always @ (posedge MRxClk or posedge Reset)
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begin
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if(Reset)
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begin
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RxStatusWriteLatched_sync1 <=#Tp 1'b0;
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RxStatusWriteLatched_sync2 <=#Tp 1'b0;
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end
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else
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begin
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RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched;
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RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1;
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end
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end
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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if(Reset)
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begin
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RxStatusWriteLatched_syncb1 <=#Tp 1'b0;
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RxStatusWriteLatched_syncb2 <=#Tp 1'b0;
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end
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else
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begin
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RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2;
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RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1;
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end
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end
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// Tx Done Interrupt
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// Tx Done Interrupt
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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TxB_IRQ <=#Tp 1'b0;
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TxB_IRQ <=#Tp 1'b0;
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