OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 270 and 272

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 270 Rev 272
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.49  2003/01/21 12:09:40  mohor
 
// When receiving normal data frame and RxFlow control was switched on, RXB
 
// interrupt was not set.
 
//
// Revision 1.48  2003/01/20 12:05:26  mohor
// Revision 1.48  2003/01/20 12:05:26  mohor
// When in full duplex, transmit was sometimes blocked. Fixed.
// When in full duplex, transmit was sometimes blocked. Fixed.
//
//
// Revision 1.47  2002/11/22 13:26:21  mohor
// Revision 1.47  2002/11/22 13:26:21  mohor
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
Line 242... Line 246...
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
    TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
    PerPacketPad,
    PerPacketPad,
 
 
    //RX
    //RX
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
 
 
    // Register
    // Register
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow, r_PassAll,
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow, r_PassAll,
 
 
    // Interrupts
    // Interrupts
Line 349... Line 353...
input   [7:0]   RxData;         // Received data byte (from PHY)
input   [7:0]   RxData;         // Received data byte (from PHY)
input           RxValid;        // 
input           RxValid;        // 
input           RxStartFrm;     // 
input           RxStartFrm;     // 
input           RxEndFrm;       // 
input           RxEndFrm;       // 
input           RxAbort;        // This signal is set when address doesn't match.
input           RxAbort;        // This signal is set when address doesn't match.
 
output          RxStatusWriteLatched_sync2;
 
 
//Register
//Register
input           r_TxEn;         // Transmit enable
input           r_TxEn;         // Transmit enable
input           r_RxEn;         // Receive enable
input           r_RxEn;         // Receive enable
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
Line 415... Line 420...
reg             RxBDReady;
reg             RxBDReady;
reg             RxReady;
reg             RxReady;
reg             TxBDReady;
reg             TxBDReady;
 
 
reg             RxBDRead;
reg             RxBDRead;
wire            RxStatusWrite;
 
 
 
reg    [31:0]   TxDataLatched;
reg    [31:0]   TxDataLatched;
reg     [1:0]   TxByteCnt;
reg     [1:0]   TxByteCnt;
reg             LastWord;
reg             LastWord;
reg             ReadTxDataFromFifo_tck;
reg             ReadTxDataFromFifo_tck;
Line 483... Line 487...
wire    [7:0]   TempRxBDAddress;
wire    [7:0]   TempRxBDAddress;
 
 
wire            SetGotData;
wire            SetGotData;
wire            GotDataEvaluate;
wire            GotDataEvaluate;
 
 
 
wire            RxStatusWrite;
 
 
reg             WB_ACK_O;
reg             WB_ACK_O;
 
 
wire    [8:0]   RxStatusIn;
wire    [8:0]   RxStatusIn;
reg     [8:0]   RxStatusInLatched;
reg     [8:0]   RxStatusInLatched;
 
 
Line 720... Line 726...
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    BlockingTxStatusWrite <=#Tp 1'b0;
    BlockingTxStatusWrite <=#Tp 1'b0;
  else
  else
  if(TxStatusWrite)
 
    BlockingTxStatusWrite <=#Tp 1'b1;
 
  else
 
  if(~TxDone_wb & ~TxAbort_wb)
  if(~TxDone_wb & ~TxAbort_wb)
    BlockingTxStatusWrite <=#Tp 1'b0;
    BlockingTxStatusWrite <=#Tp 1'b0;
 
  else
 
  if(TxStatusWrite)
 
    BlockingTxStatusWrite <=#Tp 1'b1;
end
end
 
 
 
 
reg BlockingTxStatusWrite_sync1;
reg BlockingTxStatusWrite_sync1;
reg BlockingTxStatusWrite_sync2;
reg BlockingTxStatusWrite_sync2;
Line 1430... Line 1436...
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    TxAbortPacket_NotCleared <=#Tp 1'b0;
    TxAbortPacket_NotCleared <=#Tp 1'b0;
  else
  else
 
  if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
 
    TxAbortPacket_NotCleared <=#Tp 1'b0;
 
  else
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
  if(TxAbort_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
     TxAbort_wb & !MasterWbTX)
     TxAbort_wb & !MasterWbTX)
    TxAbortPacket_NotCleared <=#Tp 1'b1;
    TxAbortPacket_NotCleared <=#Tp 1'b1;
  else
 
    TxAbortPacket_NotCleared <=#Tp 1'b0;
 
end
end
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
Line 1470... Line 1477...
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    TxRetryPacket_NotCleared <=#Tp 1'b0;
    TxRetryPacket_NotCleared <=#Tp 1'b0;
  else
  else
 
  if(StartTxBDRead)
 
    TxRetryPacket_NotCleared <=#Tp 1'b0;
 
  else
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
  if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
     TxRetry_wb & !MasterWbTX)
     TxRetry_wb & !MasterWbTX)
    TxRetryPacket_NotCleared <=#Tp 1'b1;
    TxRetryPacket_NotCleared <=#Tp 1'b1;
  else
 
    TxRetryPacket_NotCleared <=#Tp 1'b0;
 
end
end
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
Line 1510... Line 1518...
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    TxDonePacket_NotCleared <=#Tp 1'b0;
    TxDonePacket_NotCleared <=#Tp 1'b0;
  else
  else
 
  if(TxEn & TxEn_q & TxDonePacket_NotCleared)
 
    TxDonePacket_NotCleared <=#Tp 1'b0;
 
  else
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
  if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
     TxDone_wb & !MasterWbTX)
     TxDone_wb & !MasterWbTX)
    TxDonePacket_NotCleared <=#Tp 1'b1;
    TxDonePacket_NotCleared <=#Tp 1'b1;
  else
 
    TxDonePacket_NotCleared <=#Tp 1'b0;
 
end
end
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
Line 2390... Line 2399...
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
// are aborted when signal r_RecSmall is set to 0 in MODER register. 
// AddressMiss is identifying that a frame was received because of the promiscous
// AddressMiss is identifying that a frame was received because of the promiscous
// mode and is not an error
// mode and is not an error
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
 
 
 
 
 
 
 
reg RxStatusWriteLatched;
 
reg RxStatusWriteLatched_sync1;
 
reg RxStatusWriteLatched_sync2;
 
reg RxStatusWriteLatched_syncb1;
 
reg RxStatusWriteLatched_syncb2;
 
 
 
 
 
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
  if(Reset)
 
    RxStatusWriteLatched <=#Tp 1'b0;
 
  else
 
  if(RxStatusWriteLatched_syncb2)
 
    RxStatusWriteLatched <=#Tp 1'b0;
 
  else
 
  if(RxStatusWrite)
 
    RxStatusWriteLatched <=#Tp 1'b1;
 
end
 
 
 
 
 
always @ (posedge MRxClk or posedge Reset)
 
begin
 
  if(Reset)
 
    begin
 
      RxStatusWriteLatched_sync1 <=#Tp 1'b0;
 
      RxStatusWriteLatched_sync2 <=#Tp 1'b0;
 
    end
 
  else
 
    begin
 
      RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched;
 
      RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1;
 
    end
 
end
 
 
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
 
begin
 
  if(Reset)
 
    begin
 
      RxStatusWriteLatched_syncb1 <=#Tp 1'b0;
 
      RxStatusWriteLatched_syncb2 <=#Tp 1'b0;
 
    end
 
  else
 
    begin
 
      RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2;
 
      RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1;
 
    end
 
end
 
 
 
 
 
 
// Tx Done Interrupt
// Tx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    TxB_IRQ <=#Tp 1'b0;
    TxB_IRQ <=#Tp 1'b0;

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.