| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.54 2003/11/12 18:24:59 tadejm
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// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
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//
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// Revision 1.53 2003/10/17 07:46:17 markom
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// Revision 1.53 2003/10/17 07:46:17 markom
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// mbist signals updated according to newest convention
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// mbist signals updated according to newest convention
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//
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//
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// Revision 1.52 2003/01/30 14:51:31 mohor
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// Revision 1.52 2003/01/30 14:51:31 mohor
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// Reset has priority in some flipflops.
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// Reset has priority in some flipflops.
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| Line 262... |
Line 265... |
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//RX
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//RX
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MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
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MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
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// Register
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// Register
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r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow, r_PassAll,
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r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
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// Interrupts
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// Interrupts
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
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// Rx Status
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// Rx Status
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| Line 370... |
Line 373... |
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//Register
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//Register
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input r_TxEn; // Transmit enable
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input r_TxEn; // Transmit enable
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input r_RxEn; // Receive enable
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input r_RxEn; // Receive enable
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input [7:0] r_TxBDNum; // Receive buffer descriptor number
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input [7:0] r_TxBDNum; // Receive buffer descriptor number
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input TX_BD_NUM_Wr; // RxBDNumber written
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// Interrupts
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// Interrupts
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output TxB_IRQ;
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output TxB_IRQ;
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output TxE_IRQ;
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output TxE_IRQ;
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output RxB_IRQ;
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output RxB_IRQ;
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| Line 503... |
Line 505... |
reg [8:0] RxStatusInLatched;
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reg [8:0] RxStatusInLatched;
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reg WbEn, WbEn_q;
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reg WbEn, WbEn_q;
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reg RxEn, RxEn_q;
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reg RxEn, RxEn_q;
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reg TxEn, TxEn_q;
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reg TxEn, TxEn_q;
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reg r_TxEn_q;
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reg r_RxEn_q;
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wire ram_ce;
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wire ram_ce;
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wire [3:0] ram_we;
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wire [3:0] ram_we;
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wire ram_oe;
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wire ram_oe;
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reg [7:0] ram_addr;
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reg [7:0] ram_addr;
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| Line 647... |
Line 651... |
if(Reset)
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if(Reset)
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begin
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begin
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WbEn_q <=#Tp 1'b0;
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WbEn_q <=#Tp 1'b0;
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RxEn_q <=#Tp 1'b0;
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RxEn_q <=#Tp 1'b0;
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TxEn_q <=#Tp 1'b0;
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TxEn_q <=#Tp 1'b0;
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r_TxEn_q <=#Tp 1'b0;
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r_RxEn_q <=#Tp 1'b0;
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end
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end
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else
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else
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begin
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begin
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WbEn_q <=#Tp WbEn;
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WbEn_q <=#Tp WbEn;
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RxEn_q <=#Tp RxEn;
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RxEn_q <=#Tp RxEn;
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TxEn_q <=#Tp TxEn;
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TxEn_q <=#Tp TxEn;
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r_RxEn_q <=#Tp r_RxEn;
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end
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end
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end
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end
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// Changes for tx occur every second clock. Flop is used for this manner.
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// Changes for tx occur every second clock. Flop is used for this manner.
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always @ (posedge MTxClk or posedge Reset)
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always @ (posedge MTxClk or posedge Reset)
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| Line 1338... |
Line 1345... |
// Latching Tx buffer descriptor address
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// Latching Tx buffer descriptor address
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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TxBDAddress <=#Tp 8'h0;
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TxBDAddress <=#Tp 8'h0;
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else
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else if (r_TxEn & (~r_TxEn_q))
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if(TxStatusWrite)
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TxBDAddress <=#Tp 8'h0;
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else if (TxStatusWrite)
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TxBDAddress <=#Tp TempTxBDAddress;
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TxBDAddress <=#Tp TempTxBDAddress;
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end
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end
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// Latching Rx buffer descriptor address
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// Latching Rx buffer descriptor address
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF_0 << 1;
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RxBDAddress <=#Tp 8'h0;
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else
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else if(r_RxEn & (~r_RxEn_q))
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if(TX_BD_NUM_Wr) // When r_TxBDNum is updated, RxBDAddress is also
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RxBDAddress <=#Tp r_TxBDNum << 1;
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RxBDAddress <=#Tp WB_DAT_I[7:0] << 1;
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else if(RxStatusWrite)
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else
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if(RxStatusWrite)
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RxBDAddress <=#Tp TempRxBDAddress;
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RxBDAddress <=#Tp TempRxBDAddress;
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end
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end
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wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
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wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
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