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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 304 and 321

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Rev 304 Rev 321
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.54  2003/11/12 18:24:59  tadejm
 
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
 
//
// Revision 1.53  2003/10/17 07:46:17  markom
// Revision 1.53  2003/10/17 07:46:17  markom
// mbist signals updated according to newest convention
// mbist signals updated according to newest convention
//
//
// Revision 1.52  2003/01/30 14:51:31  mohor
// Revision 1.52  2003/01/30 14:51:31  mohor
// Reset has priority in some flipflops.
// Reset has priority in some flipflops.
Line 262... Line 265...
 
 
    //RX
    //RX
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
 
 
    // Register
    // Register
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RxFlow, r_PassAll,
    r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
 
 
    // Interrupts
    // Interrupts
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
 
 
    // Rx Status
    // Rx Status
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//Register
//Register
input           r_TxEn;         // Transmit enable
input           r_TxEn;         // Transmit enable
input           r_RxEn;         // Receive enable
input           r_RxEn;         // Receive enable
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
input           TX_BD_NUM_Wr;   // RxBDNumber written
 
 
 
// Interrupts
// Interrupts
output TxB_IRQ;
output TxB_IRQ;
output TxE_IRQ;
output TxE_IRQ;
output RxB_IRQ;
output RxB_IRQ;
Line 503... Line 505...
reg     [8:0]   RxStatusInLatched;
reg     [8:0]   RxStatusInLatched;
 
 
reg WbEn, WbEn_q;
reg WbEn, WbEn_q;
reg RxEn, RxEn_q;
reg RxEn, RxEn_q;
reg TxEn, TxEn_q;
reg TxEn, TxEn_q;
 
reg r_TxEn_q;
 
reg r_RxEn_q;
 
 
wire ram_ce;
wire ram_ce;
wire [3:0]  ram_we;
wire [3:0]  ram_we;
wire ram_oe;
wire ram_oe;
reg [7:0]   ram_addr;
reg [7:0]   ram_addr;
Line 647... Line 651...
  if(Reset)
  if(Reset)
    begin
    begin
      WbEn_q <=#Tp 1'b0;
      WbEn_q <=#Tp 1'b0;
      RxEn_q <=#Tp 1'b0;
      RxEn_q <=#Tp 1'b0;
      TxEn_q <=#Tp 1'b0;
      TxEn_q <=#Tp 1'b0;
 
      r_TxEn_q <=#Tp 1'b0;
 
      r_RxEn_q <=#Tp 1'b0;
    end
    end
  else
  else
    begin
    begin
      WbEn_q <=#Tp WbEn;
      WbEn_q <=#Tp WbEn;
      RxEn_q <=#Tp RxEn;
      RxEn_q <=#Tp RxEn;
      TxEn_q <=#Tp TxEn;
      TxEn_q <=#Tp TxEn;
 
      r_RxEn_q <=#Tp r_RxEn;
    end
    end
end
end
 
 
// Changes for tx occur every second clock. Flop is used for this manner.
// Changes for tx occur every second clock. Flop is used for this manner.
always @ (posedge MTxClk or posedge Reset)
always @ (posedge MTxClk or posedge Reset)
Line 1338... Line 1345...
// Latching Tx buffer descriptor address
// Latching Tx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    TxBDAddress <=#Tp 8'h0;
    TxBDAddress <=#Tp 8'h0;
  else
  else if (r_TxEn & (~r_TxEn_q))
  if(TxStatusWrite)
    TxBDAddress <=#Tp 8'h0;
 
  else if (TxStatusWrite)
    TxBDAddress <=#Tp TempTxBDAddress;
    TxBDAddress <=#Tp TempTxBDAddress;
end
end
 
 
 
 
// Latching Rx buffer descriptor address
// Latching Rx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
always @ (posedge WB_CLK_I or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF_0 << 1;
    RxBDAddress <=#Tp 8'h0;
  else
  else if(r_RxEn & (~r_RxEn_q))
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
    RxBDAddress <=#Tp r_TxBDNum << 1;
    RxBDAddress <=#Tp WB_DAT_I[7:0] << 1;
  else if(RxStatusWrite)
  else
 
  if(RxStatusWrite)
 
    RxBDAddress <=#Tp TempRxBDAddress;
    RxBDAddress <=#Tp TempRxBDAddress;
end
end
 
 
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
 
 

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