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https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 321 and 323
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Rev 323 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.55 2004/04/26 15:26:23 igorm
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// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
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// previous update of the core.
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// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
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// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
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// register. (thanks to Mathias and Torbjorn)
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// - Multicast reception was fixed. Thanks to Ulrich Gries
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//
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// Revision 1.54 2003/11/12 18:24:59 tadejm
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// Revision 1.54 2003/11/12 18:24:59 tadejm
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// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
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// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
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//
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//
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// Revision 1.53 2003/10/17 07:46:17 markom
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// Revision 1.53 2003/10/17 07:46:17 markom
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// mbist signals updated according to newest convention
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// mbist signals updated according to newest convention
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Line 667... |
else
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else
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begin
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begin
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WbEn_q <=#Tp WbEn;
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WbEn_q <=#Tp WbEn;
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RxEn_q <=#Tp RxEn;
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RxEn_q <=#Tp RxEn;
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TxEn_q <=#Tp TxEn;
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TxEn_q <=#Tp TxEn;
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r_TxEn_q <=#Tp r_TxEn;
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r_RxEn_q <=#Tp r_RxEn;
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r_RxEn_q <=#Tp r_RxEn;
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end
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end
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end
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end
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// Changes for tx occur every second clock. Flop is used for this manner.
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// Changes for tx occur every second clock. Flop is used for this manner.
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