OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 346 and 349

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 346 Rev 349
Line 307... Line 307...
 
 
                );
                );
 
 
 
 
parameter Tp = 1;
parameter Tp = 1;
 
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
 
parameter TX_FIFO_DEPTH      = `ETH_TX_FIFO_DEPTH;
 
parameter TX_FIFO_CNT_WIDTH  = `ETH_TX_FIFO_CNT_WIDTH;
 
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
 
parameter RX_FIFO_DEPTH      = `ETH_RX_FIFO_DEPTH;
 
parameter RX_FIFO_CNT_WIDTH  = `ETH_RX_FIFO_CNT_WIDTH;
 
 
 
 
// WISHBONE common
// WISHBONE common
input           WB_CLK_I;       // WISHBONE clock
input           WB_CLK_I;       // WISHBONE clock
input  [31:0]   WB_DAT_I;       // WISHBONE data input
input  [31:0]   WB_DAT_I;       // WISHBONE data input
Line 1004... Line 1010...
    BlockReadTxDataFromMemory <=#Tp 1'b0;
    BlockReadTxDataFromMemory <=#Tp 1'b0;
end
end
 
 
 
 
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
wire [TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
wire [RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
reg  [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
reg  [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
 
 
wire rx_burst;
wire rx_burst;
wire enough_data_in_rxfifo_for_burst;
wire enough_data_in_rxfifo_for_burst;
Line 1156... Line 1162...
          begin
          begin
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
            cyc_cleared<=#Tp 1'b1;
            cyc_cleared<=#Tp 1'b1;
            IncrTxPointer<=#Tp 1'b0;
            IncrTxPointer<=#Tp 1'b0;
            tx_burst_cnt<=#Tp 0;
            tx_burst_cnt<=#Tp 0;
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
            tx_burst_en<=#Tp txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
            rx_burst_cnt<=#Tp 0;
            rx_burst_cnt<=#Tp 0;
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
            rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst;  // Counter is not decremented, yet, so plus1 is used.
            `ifdef ETH_WISHBONE_B3
            `ifdef ETH_WISHBONE_B3
              m_wb_cti_o <=#Tp 3'b0;
              m_wb_cti_o <=#Tp 3'b0;
            `endif
            `endif
Line 1180... Line 1186...
            `endif
            `endif
          end
          end
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
        8'b00_00_00_00:             // whatever and no master read or write is needed (ack or err comes finishing previous access)
          begin
          begin
            tx_burst_cnt<=#Tp 0;
            tx_burst_cnt<=#Tp 0;
            tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
            tx_burst_en<=#Tp txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
          end
          end
        default:                    // Don't touch
        default:                    // Don't touch
          begin
          begin
            MasterWbTX <=#Tp MasterWbTX;
            MasterWbTX <=#Tp MasterWbTX;
            MasterWbRX <=#Tp MasterWbRX;
            MasterWbRX <=#Tp MasterWbRX;
Line 1199... Line 1205...
 
 
wire TxFifoClear;
wire TxFifoClear;
 
 
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
 
 
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
eth_fifo #(.DATA_WIDTH(TX_FIFO_DATA_WIDTH),
 
           .DEPTH(TX_FIFO_DEPTH),
 
           .CNT_WIDTH(TX_FIFO_CNT_WIDTH),
 
           .Tp(Tp))
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
tx_fifo ( .data_in(m_wb_dat_i),                             .data_out(TxData_wb),
          .clk(WB_CLK_I),                                   .reset(Reset),
          .clk(WB_CLK_I),                                   .reset(Reset),
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
          .write(MasterWbTX & m_wb_ack_i),                  .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
          .clear(TxFifoClear),                              .full(TxBufferFull),
          .clear(TxFifoClear),                              .full(TxBufferFull),
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
Line 2194... Line 2203...
end
end
 
 
 
 
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
 
 
 
eth_fifo #(.DATA_WIDTH(RX_FIFO_DATA_WIDTH),
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
           .DEPTH(RX_FIFO_DEPTH),
 
           .CNT_WIDTH(RX_FIFO_CNT_WIDTH),
 
           .Tp(Tp))
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
         .clk(WB_CLK_I),                                .reset(Reset),
         .clk(WB_CLK_I),                                .reset(Reset),
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
         .write(WriteRxDataToFifo_wb & ~RxBufferFull),  .read(MasterWbRX & m_wb_ack_i),
         .clear(RxFifoReset),                           .full(RxBufferFull),
         .clear(RxFifoReset),                           .full(RxBufferFull),
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.