| Line 276... |
Line 276... |
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
|
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
|
TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
|
TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
|
PerPacketPad,
|
PerPacketPad,
|
|
|
//RX
|
//RX
|
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
|
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
|
|
RxStatusWriteLatched_sync2,
|
|
|
// Register
|
// Register
|
r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
|
r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
|
|
|
// Interrupts
|
// Interrupts
|
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
|
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
|
|
|
// Rx Status
|
// Rx Status
|
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
|
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
|
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
|
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
|
|
AddressMiss,
|
ReceivedPauseFrm,
|
ReceivedPauseFrm,
|
|
|
// Tx Status
|
// Tx Status
|
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost
|
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched,
|
|
CarrierSenseLost
|
|
|
// Bist
|
// Bist
|
`ifdef ETH_BIST
|
`ifdef ETH_BIST
|
,
|
,
|
// debug chain signals
|
// debug chain signals
|
| Line 305... |
Line 308... |
|
|
|
|
|
|
);
|
);
|
|
|
|
|
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
|
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH;
|
parameter TX_FIFO_DEPTH = `ETH_TX_FIFO_DEPTH;
|
parameter TX_FIFO_DEPTH = `ETH_TX_FIFO_DEPTH;
|
parameter TX_FIFO_CNT_WIDTH = `ETH_TX_FIFO_CNT_WIDTH;
|
parameter TX_FIFO_CNT_WIDTH = `ETH_TX_FIFO_CNT_WIDTH;
|
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
|
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH;
|
parameter RX_FIFO_DEPTH = `ETH_RX_FIFO_DEPTH;
|
parameter RX_FIFO_DEPTH = `ETH_RX_FIFO_DEPTH;
|
parameter RX_FIFO_CNT_WIDTH = `ETH_RX_FIFO_CNT_WIDTH;
|
parameter RX_FIFO_CNT_WIDTH = `ETH_RX_FIFO_CNT_WIDTH;
|
|
|
|
|
// WISHBONE common
|
// WISHBONE common
|
input WB_CLK_I; // WISHBONE clock
|
input WB_CLK_I; // WISHBONE clock
|
input [31:0] WB_DAT_I; // WISHBONE data input
|
input [31:0] WB_DAT_I; // WISHBONE data input
|
output [31:0] WB_DAT_O; // WISHBONE data output
|
output [31:0] WB_DAT_O; // WISHBONE data output
|
|
|
| Line 348... |
Line 349... |
|
|
// Rx Status signals
|
// Rx Status signals
|
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
|
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
|
input LatchedCrcError; // CRC error
|
input LatchedCrcError; // CRC error
|
input RxLateCollision; // Late collision occured while receiving frame
|
input RxLateCollision; // Late collision occured while receiving frame
|
input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
|
input ShortFrame; // Frame shorter then the minimum size
|
|
// (r_MinFL) was received while small
|
|
// packets are enabled (r_RecSmall)
|
input DribbleNibble; // Extra nibble received
|
input DribbleNibble; // Extra nibble received
|
input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
|
input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
|
input [15:0] RxLength; // Length of the incoming frame
|
input [15:0] RxLength; // Length of the incoming frame
|
input LoadRxStatus; // Rx status was loaded
|
input LoadRxStatus; // Rx status was loaded
|
input ReceivedPacketGood;// Received packet's length and CRC are good
|
input ReceivedPacketGood; // Received packet's length and CRC are
|
input AddressMiss; // When a packet is received AddressMiss status is written to the Rx BD
|
// good
|
|
input AddressMiss; // When a packet is received AddressMiss
|
|
// status is written to the Rx BD
|
input r_RxFlow;
|
input r_RxFlow;
|
input r_PassAll;
|
input r_PassAll;
|
input ReceivedPauseFrm;
|
input ReceivedPauseFrm;
|
|
|
// Tx Status signals
|
// Tx Status signals
|
input [3:0] RetryCntLatched; // Latched Retry Counter
|
input [3:0] RetryCntLatched; // Latched Retry Counter
|
input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
|
input RetryLimit; // Retry limit reached (Retry Max value +1
|
|
// attempts were made)
|
input LateCollLatched; // Late collision occured
|
input LateCollLatched; // Late collision occured
|
input DeferLatched; // Defer indication (Frame was defered before sucessfully sent)
|
input DeferLatched; // Defer indication (Frame was defered
|
|
// before sucessfully sent)
|
output RstDeferLatched;
|
output RstDeferLatched;
|
input CarrierSenseLost; // Carrier Sense was lost during the frame transmission
|
input CarrierSenseLost; // Carrier Sense was lost during the
|
|
// frame transmission
|
|
|
// Tx
|
// Tx
|
input MTxClk; // Transmit clock (from PHY)
|
input MTxClk; // Transmit clock (from PHY)
|
input TxUsedData; // Transmit packet used data
|
input TxUsedData; // Transmit packet used data
|
input TxRetry; // Transmit packet retry
|
input TxRetry; // Transmit packet retry
|
| Line 386... |
Line 394... |
input MRxClk; // Receive clock (from PHY)
|
input MRxClk; // Receive clock (from PHY)
|
input [7:0] RxData; // Received data byte (from PHY)
|
input [7:0] RxData; // Received data byte (from PHY)
|
input RxValid; //
|
input RxValid; //
|
input RxStartFrm; //
|
input RxStartFrm; //
|
input RxEndFrm; //
|
input RxEndFrm; //
|
input RxAbort; // This signal is set when address doesn't match.
|
input RxAbort; // This signal is set when address doesn't
|
|
// match.
|
output RxStatusWriteLatched_sync2;
|
output RxStatusWriteLatched_sync2;
|
|
|
//Register
|
//Register
|
input r_TxEn; // Transmit enable
|
input r_TxEn; // Transmit enable
|
input r_RxEn; // Receive enable
|
input r_RxEn; // Receive enable
|
| Line 546... |
Line 555... |
reg RxEn_needed;
|
reg RxEn_needed;
|
|
|
wire StartRxPointerRead;
|
wire StartRxPointerRead;
|
reg RxPointerRead;
|
reg RxPointerRead;
|
|
|
|
// RX shift ending signals
|
|
reg ShiftEnded_rck;
|
|
reg ShiftEndedSync1;
|
|
reg ShiftEndedSync2;
|
|
reg ShiftEndedSync3;
|
|
reg ShiftEndedSync_c1;
|
|
reg ShiftEndedSync_c2;
|
|
|
|
wire StartShiftWillEnd;
|
|
|
|
reg StartOccured;
|
|
reg TxStartFrm_sync1;
|
|
reg TxStartFrm_sync2;
|
|
reg TxStartFrm_syncb1;
|
|
reg TxStartFrm_syncb2;
|
|
|
|
wire TxFifoClear;
|
|
wire TxBufferAlmostFull;
|
|
wire TxBufferFull;
|
|
wire TxBufferEmpty;
|
|
wire TxBufferAlmostEmpty;
|
|
wire SetReadTxDataFromMemory;
|
|
reg BlockReadTxDataFromMemory;
|
|
|
|
reg tx_burst_en;
|
|
reg rx_burst_en;
|
|
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
|
|
|
|
wire ReadTxDataFromMemory_2;
|
|
wire tx_burst;
|
|
|
|
wire [31:0] TxData_wb;
|
|
wire ReadTxDataFromFifo_wb;
|
|
|
|
wire [TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
|
|
wire [RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
|
|
|
|
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
|
|
|
|
wire rx_burst;
|
|
wire enough_data_in_rxfifo_for_burst;
|
|
wire enough_data_in_rxfifo_for_burst_plus1;
|
|
|
|
reg ReadTxDataFromMemory;
|
|
wire WriteRxDataToMemory;
|
|
|
|
reg MasterWbTX;
|
|
reg MasterWbRX;
|
|
|
|
reg [29:0] m_wb_adr_o;
|
|
reg m_wb_cyc_o;
|
|
reg [3:0] m_wb_sel_o;
|
|
reg m_wb_we_o;
|
|
|
|
wire TxLengthEq0;
|
|
wire TxLengthLt4;
|
|
|
|
reg BlockingIncrementTxPointer;
|
|
reg [31:2] TxPointerMSB;
|
|
reg [1:0] TxPointerLSB;
|
|
reg [1:0] TxPointerLSB_rst;
|
|
reg [31:2] RxPointerMSB;
|
|
reg [1:0] RxPointerLSB_rst;
|
|
|
|
wire RxBurstAcc;
|
|
wire RxWordAcc;
|
|
wire RxHalfAcc;
|
|
wire RxByteAcc;
|
|
|
|
wire ResetTxBDReady;
|
|
reg BlockingTxStatusWrite_sync1;
|
|
reg BlockingTxStatusWrite_sync2;
|
|
reg BlockingTxStatusWrite_sync3;
|
|
|
|
reg cyc_cleared;
|
|
reg IncrTxPointer;
|
|
|
|
reg [3:0] RxByteSel;
|
|
wire MasterAccessFinished;
|
|
|
|
reg LatchValidBytes;
|
|
reg LatchValidBytes_q;
|
|
|
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
|
reg ReadTxDataFromFifo_sync1;
|
|
reg ReadTxDataFromFifo_sync2;
|
|
reg ReadTxDataFromFifo_sync3;
|
|
reg ReadTxDataFromFifo_syncb1;
|
|
reg ReadTxDataFromFifo_syncb2;
|
|
reg ReadTxDataFromFifo_syncb3;
|
|
|
|
reg RxAbortSync1;
|
|
reg RxAbortSync2;
|
|
reg RxAbortSync3;
|
|
reg RxAbortSync4;
|
|
reg RxAbortSyncb1;
|
|
reg RxAbortSyncb2;
|
|
|
|
reg RxEnableWindow;
|
|
|
|
wire SetWriteRxDataToFifo;
|
|
|
|
reg WriteRxDataToFifoSync1;
|
|
reg WriteRxDataToFifoSync2;
|
|
reg WriteRxDataToFifoSync3;
|
|
|
|
wire WriteRxDataToFifo_wb;
|
|
|
|
reg LatchedRxStartFrm;
|
|
reg SyncRxStartFrm;
|
|
reg SyncRxStartFrm_q;
|
|
reg SyncRxStartFrm_q2;
|
|
wire RxFifoReset;
|
|
|
|
wire TxError;
|
|
wire RxError;
|
|
|
|
reg RxStatusWriteLatched;
|
|
reg RxStatusWriteLatched_sync1;
|
|
reg RxStatusWriteLatched_sync2;
|
|
reg RxStatusWriteLatched_syncb1;
|
|
reg RxStatusWriteLatched_syncb2;
|
|
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
assign m_wb_bte_o = 2'b00; // Linear burst
|
assign m_wb_bte_o = 2'b00; // Linear burst
|
`endif
|
`endif
|
|
|
assign m_wb_stb_o = m_wb_cyc_o;
|
assign m_wb_stb_o = m_wb_cyc_o;
|
| Line 560... |
Line 692... |
end
|
end
|
|
|
assign WB_DAT_O = ram_do;
|
assign WB_DAT_O = ram_do;
|
|
|
// Generic synchronous single-port RAM interface
|
// Generic synchronous single-port RAM interface
|
eth_spram_256x32 bd_ram (
|
eth_spram_256x32
|
.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
|
bd_ram
|
|
(
|
|
.clk (WB_CLK_I),
|
|
.rst (Reset),
|
|
.ce (ram_ce),
|
|
.we (ram_we),
|
|
.oe (ram_oe),
|
|
.addr (ram_addr),
|
|
.di (ram_di),
|
|
.do (ram_do)
|
`ifdef ETH_BIST
|
`ifdef ETH_BIST
|
,
|
,
|
.mbist_si_i (mbist_si_i),
|
.mbist_si_i (mbist_si_i),
|
.mbist_so_o (mbist_so_o),
|
.mbist_so_o (mbist_so_o),
|
.mbist_ctrl_i (mbist_ctrl_i)
|
.mbist_ctrl_i (mbist_ctrl_i)
|
`endif
|
`endif
|
);
|
);
|
|
|
assign ram_ce = 1'b1;
|
assign ram_ce = 1'b1;
|
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | {4{(TxStatusWrite | RxStatusWrite)}};
|
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) |
|
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
|
{4{(TxStatusWrite | RxStatusWrite)}};
|
|
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q &
|
|
(TxBDRead | TxPointerRead) | RxEn & RxEn_q &
|
|
(RxBDRead | RxPointerRead);
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 616... |
Line 760... |
end
|
end
|
5'b100_01 :
|
5'b100_01 :
|
begin
|
begin
|
WbEn <= 1'b0;
|
WbEn <= 1'b0;
|
RxEn <= 1'b0;
|
RxEn <= 1'b0;
|
TxEn <= 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
|
TxEn <= 1'b1; // wb access stage, r_RxEn is disabled but
|
|
// r_TxEn is enabled
|
ram_addr <= {TxBDAddress, TxPointerRead};
|
ram_addr <= {TxBDAddress, TxPointerRead};
|
ram_di <= TxBDDataIn;
|
ram_di <= TxBDDataIn;
|
end
|
end
|
5'b010_00, 5'b010_10 :
|
5'b010_00, 5'b010_10 :
|
begin
|
begin
|
| Line 640... |
Line 785... |
ram_addr <= {TxBDAddress, TxPointerRead};
|
ram_addr <= {TxBDAddress, TxPointerRead};
|
ram_di <= TxBDDataIn;
|
ram_di <= TxBDDataIn;
|
end
|
end
|
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
|
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
|
begin
|
begin
|
WbEn <= 1'b1; // TxEn access stage (we always go to wb access stage)
|
WbEn <= 1'b1; // TxEn access stage (we always go to wb
|
|
// access stage)
|
RxEn <= 1'b0;
|
RxEn <= 1'b0;
|
TxEn <= 1'b0;
|
TxEn <= 1'b0;
|
ram_addr <= WB_ADR_I[9:2];
|
ram_addr <= WB_ADR_I[9:2];
|
ram_di <= WB_DAT_I;
|
ram_di <= WB_DAT_I;
|
BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
|
BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
|
BDRead <= (|BDCs) & ~WB_WE_I;
|
BDRead <= (|BDCs) & ~WB_WE_I;
|
end
|
end
|
5'b100_00 :
|
5'b100_00 :
|
begin
|
begin
|
WbEn <= 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
|
WbEn <= 1'b0; // WbEn access stage and there is no need
|
|
// for other stages. WbEn needs to be
|
|
// switched off for a bit
|
end
|
end
|
5'b000_00 :
|
5'b000_00 :
|
begin
|
begin
|
WbEn <= 1'b1; // Idle state. We go to WbEn access stage.
|
WbEn <= 1'b1; // Idle state. We go to WbEn access stage.
|
RxEn <= 1'b0;
|
RxEn <= 1'b0;
|
| Line 701... |
Line 849... |
else
|
else
|
if(TxUsedData)
|
if(TxUsedData)
|
Flop <= ~Flop;
|
Flop <= ~Flop;
|
end
|
end
|
|
|
wire ResetTxBDReady;
|
|
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
|
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
|
|
|
// Latching READY status of the Tx buffer descriptor
|
// Latching READY status of the Tx buffer descriptor
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxBDReady <= 1'b0;
|
TxBDReady <= 1'b0;
|
else
|
else
|
if(TxEn & TxEn_q & TxBDRead)
|
if(TxEn & TxEn_q & TxBDRead)
|
TxBDReady <= ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
|
// TxBDReady is sampled only once at the beginning.
|
else // Only packets larger then 4 bytes are transmitted.
|
TxBDReady <= ram_do[15] & (ram_do[31:16] > 4);
|
|
else
|
|
// Only packets larger then 4 bytes are transmitted.
|
if(ResetTxBDReady)
|
if(ResetTxBDReady)
|
TxBDReady <= 1'b0;
|
TxBDReady <= 1'b0;
|
end
|
end
|
|
|
|
|
// Reading the Tx buffer descriptor
|
// Reading the Tx buffer descriptor
|
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
|
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) &
|
|
~BlockingTxBDRead & ~TxBDReady;
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxBDRead <= 1'b1;
|
TxBDRead <= 1'b1;
|
| Line 733... |
Line 882... |
else
|
else
|
if(TxBDReady)
|
if(TxBDReady)
|
TxBDRead <= 1'b0;
|
TxBDRead <= 1'b0;
|
end
|
end
|
|
|
|
|
// Reading Tx BD pointer
|
// Reading Tx BD pointer
|
assign StartTxPointerRead = TxBDRead & TxBDReady;
|
assign StartTxPointerRead = TxBDRead & TxBDReady;
|
|
|
// Reading Tx BD Pointer
|
// Reading Tx BD Pointer
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
| Line 752... |
Line 900... |
TxPointerRead <= 1'b0;
|
TxPointerRead <= 1'b0;
|
end
|
end
|
|
|
|
|
// Writing status back to the Tx buffer descriptor
|
// Writing status back to the Tx buffer descriptor
|
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
|
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) &
|
|
TxEn & TxEn_q & ~BlockingTxStatusWrite;
|
|
|
|
|
// Status writing must occur only once. Meanwhile it is blocked.
|
// Status writing must occur only once. Meanwhile it is blocked.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
| Line 770... |
Line 918... |
if(TxStatusWrite)
|
if(TxStatusWrite)
|
BlockingTxStatusWrite <= 1'b1;
|
BlockingTxStatusWrite <= 1'b1;
|
end
|
end
|
|
|
|
|
reg BlockingTxStatusWrite_sync1;
|
|
reg BlockingTxStatusWrite_sync2;
|
|
reg BlockingTxStatusWrite_sync3;
|
|
|
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
BlockingTxStatusWrite_sync1 <= 1'b0;
|
BlockingTxStatusWrite_sync1 <= 1'b0;
|
| Line 801... |
Line 945... |
BlockingTxStatusWrite_sync3 <= 1'b0;
|
BlockingTxStatusWrite_sync3 <= 1'b0;
|
else
|
else
|
BlockingTxStatusWrite_sync3 <= BlockingTxStatusWrite_sync2;
|
BlockingTxStatusWrite_sync3 <= BlockingTxStatusWrite_sync2;
|
end
|
end
|
|
|
assign RstDeferLatched = BlockingTxStatusWrite_sync2 & ~BlockingTxStatusWrite_sync3;
|
assign RstDeferLatched = BlockingTxStatusWrite_sync2 &
|
|
~BlockingTxStatusWrite_sync3;
|
|
|
// TxBDRead state is activated only once.
|
// TxBDRead state is activated only once.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 818... |
Line 963... |
BlockingTxBDRead <= 1'b0;
|
BlockingTxBDRead <= 1'b0;
|
end
|
end
|
|
|
|
|
// Latching status from the tx buffer descriptor
|
// Latching status from the tx buffer descriptor
|
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
|
// Data is avaliable one cycle after the access is started (at that time
|
|
// signal TxEn is not active)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxStatus <= 4'h0;
|
TxStatus <= 4'h0;
|
else
|
else
|
if(TxEn & TxEn_q & TxBDRead)
|
if(TxEn & TxEn_q & TxBDRead)
|
TxStatus <= ram_do[14:11];
|
TxStatus <= ram_do[14:11];
|
end
|
end
|
|
|
reg ReadTxDataFromMemory;
|
|
wire WriteRxDataToMemory;
|
|
|
|
reg MasterWbTX;
|
|
reg MasterWbRX;
|
|
|
|
reg [29:0] m_wb_adr_o;
|
|
reg m_wb_cyc_o;
|
|
reg [3:0] m_wb_sel_o;
|
|
reg m_wb_we_o;
|
|
|
|
wire TxLengthEq0;
|
|
wire TxLengthLt4;
|
|
|
|
reg BlockingIncrementTxPointer;
|
|
reg [31:2] TxPointerMSB;
|
|
reg [1:0] TxPointerLSB;
|
|
reg [1:0] TxPointerLSB_rst;
|
|
reg [31:2] RxPointerMSB;
|
|
reg [1:0] RxPointerLSB_rst;
|
|
|
|
wire RxBurstAcc;
|
|
wire RxWordAcc;
|
|
wire RxHalfAcc;
|
|
wire RxByteAcc;
|
|
|
|
//Latching length from the buffer descriptor;
|
//Latching length from the buffer descriptor;
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 867... |
Line 989... |
else
|
else
|
if(MasterWbTX & m_wb_ack_i)
|
if(MasterWbTX & m_wb_ack_i)
|
begin
|
begin
|
if(TxLengthLt4)
|
if(TxLengthLt4)
|
TxLength <= 16'h0;
|
TxLength <= 16'h0;
|
else
|
else if(TxPointerLSB_rst==2'h0)
|
if(TxPointerLSB_rst==2'h0)
|
TxLength <= TxLength - 3'h4; // Length is subtracted at
|
TxLength <= TxLength - 3'h4; // Length is subtracted at the data request
|
// the data request
|
else
|
else if(TxPointerLSB_rst==2'h1)
|
if(TxPointerLSB_rst==2'h1)
|
TxLength <= TxLength - 3'h3; // Length is subtracted
|
TxLength <= TxLength - 3'h3; // Length is subtracted at the data request
|
// at the data request
|
else
|
else if(TxPointerLSB_rst==2'h2)
|
if(TxPointerLSB_rst==2'h2)
|
TxLength <= TxLength - 3'h2; // Length is subtracted
|
TxLength <= TxLength - 3'h2; // Length is subtracted at the data request
|
// at the data request
|
else
|
else if(TxPointerLSB_rst==2'h3)
|
if(TxPointerLSB_rst==2'h3)
|
TxLength <= TxLength - 3'h1; // Length is subtracted
|
TxLength <= TxLength - 3'h1; // Length is subtracted at the data request
|
// at the data request
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
//Latching length from the buffer descriptor;
|
//Latching length from the buffer descriptor;
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
LatchedTxLength <= 16'h0;
|
LatchedTxLength <= 16'h0;
|
| Line 897... |
Line 1017... |
end
|
end
|
|
|
assign TxLengthEq0 = TxLength == 0;
|
assign TxLengthEq0 = TxLength == 0;
|
assign TxLengthLt4 = TxLength < 4;
|
assign TxLengthLt4 = TxLength < 4;
|
|
|
reg cyc_cleared;
|
|
reg IncrTxPointer;
|
|
|
|
|
|
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
|
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are
|
// because TxPointerMSB is only used for word-aligned accesses.
|
// latched because TxPointerMSB is only used for word-aligned accesses.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxPointerMSB <= 30'h0;
|
TxPointerMSB <= 30'h0;
|
else
|
else
|
if(TxEn & TxEn_q & TxPointerRead)
|
if(TxEn & TxEn_q & TxPointerRead)
|
TxPointerMSB <= ram_do[31:2];
|
TxPointerMSB <= ram_do[31:2];
|
else
|
else
|
if(IncrTxPointer & ~BlockingIncrementTxPointer)
|
if(IncrTxPointer & ~BlockingIncrementTxPointer)
|
TxPointerMSB <= TxPointerMSB + 1'b1; // TxPointer is word-aligned
|
// TxPointer is word-aligned
|
|
TxPointerMSB <= TxPointerMSB + 1'b1;
|
end
|
end
|
|
|
|
|
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
|
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are
|
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
|
// performed, valid data does not necesserly start at byte 0 (could be byte
|
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
|
// 0, 1, 2 or 3). This signals are used for proper selection of the start
|
// set by this two bits.
|
// byte (TxData and TxByteCnt) are set by this two bits.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxPointerLSB[1:0] <= 0;
|
TxPointerLSB[1:0] <= 0;
|
else
|
else
|
| Line 931... |
Line 1049... |
TxPointerLSB[1:0] <= ram_do[1:0];
|
TxPointerLSB[1:0] <= ram_do[1:0];
|
end
|
end
|
|
|
|
|
// Latching 2 MSB bits of the buffer descriptor.
|
// Latching 2 MSB bits of the buffer descriptor.
|
// After the read access, TxLength needs to be decremented for the number of the valid
|
// After the read access, TxLength needs to be decremented for the number of
|
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are
|
// the valid bytes (1 to 4 bytes are valid in the first word). After the
|
// valid so this two bits are reset to zero.
|
// first read all bytes are valid so this two bits are reset to zero.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxPointerLSB_rst[1:0] <= 0;
|
TxPointerLSB_rst[1:0] <= 0;
|
else
|
else
|
if(TxEn & TxEn_q & TxPointerRead)
|
if(TxEn & TxEn_q & TxPointerRead)
|
TxPointerLSB_rst[1:0] <= ram_do[1:0];
|
TxPointerLSB_rst[1:0] <= ram_do[1:0];
|
else
|
else
|
if(MasterWbTX & m_wb_ack_i) // After first access pointer is word alligned
|
// After first access pointer is word alligned
|
|
if(MasterWbTX & m_wb_ack_i)
|
TxPointerLSB_rst[1:0] <= 0;
|
TxPointerLSB_rst[1:0] <= 0;
|
end
|
end
|
|
|
|
|
reg [3:0] RxByteSel;
|
|
wire MasterAccessFinished;
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
BlockingIncrementTxPointer <= 0;
|
BlockingIncrementTxPointer <= 0;
|
else
|
else
|
| Line 964... |
Line 1079... |
if(IncrTxPointer)
|
if(IncrTxPointer)
|
BlockingIncrementTxPointer <= 1'b1;
|
BlockingIncrementTxPointer <= 1'b1;
|
end
|
end
|
|
|
|
|
wire TxBufferAlmostFull;
|
|
wire TxBufferFull;
|
|
wire TxBufferEmpty;
|
|
wire TxBufferAlmostEmpty;
|
|
wire SetReadTxDataFromMemory;
|
|
|
|
reg BlockReadTxDataFromMemory;
|
|
|
|
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
|
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 986... |
Line 1093... |
else
|
else
|
if(SetReadTxDataFromMemory)
|
if(SetReadTxDataFromMemory)
|
ReadTxDataFromMemory <= 1'b1;
|
ReadTxDataFromMemory <= 1'b1;
|
end
|
end
|
|
|
reg tx_burst_en;
|
assign ReadTxDataFromMemory_2 = ReadTxDataFromMemory &
|
reg rx_burst_en;
|
~BlockReadTxDataFromMemory;
|
|
|
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
|
assign tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
|
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
|
|
|
|
wire [31:0] TxData_wb;
|
|
wire ReadTxDataFromFifo_wb;
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
BlockReadTxDataFromMemory <= 1'b0;
|
BlockReadTxDataFromMemory <= 1'b0;
|
else
|
else
|
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
|
if((TxBufferAlmostFull | TxLength <= 4) & MasterWbTX & (~cyc_cleared) &
|
|
(!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
|
BlockReadTxDataFromMemory <= 1'b1;
|
BlockReadTxDataFromMemory <= 1'b1;
|
else
|
else
|
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
|
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
|
BlockReadTxDataFromMemory <= 1'b0;
|
BlockReadTxDataFromMemory <= 1'b0;
|
end
|
end
|
|
|
|
|
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
|
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
|
wire [TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
|
|
wire [RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
|
|
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
|
|
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
|
|
|
|
wire rx_burst;
|
|
wire enough_data_in_rxfifo_for_burst;
|
|
wire enough_data_in_rxfifo_for_burst_plus1;
|
|
|
|
// Enabling master wishbone access to the memory for two devices TX and RX.
|
// Enabling master wishbone access to the memory for two devices TX and RX.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 1042... |
Line 1138... |
`endif
|
`endif
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// Switching between two stages depends on enable signals
|
// Switching between two stages depends on enable signals
|
casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst}) // synopsys parallel_case
|
casex ({MasterWbTX,
|
|
MasterWbRX,
|
|
ReadTxDataFromMemory_2,
|
|
WriteRxDataToMemory,
|
|
MasterAccessFinished,
|
|
cyc_cleared,
|
|
tx_burst,
|
|
rx_burst}) // synopsys parallel_case
|
|
|
8'b00_10_00_10, // Idle and MRB needed
|
8'b00_10_00_10, // Idle and MRB needed
|
8'b10_1x_10_1x, // MRB continues
|
8'b10_1x_10_1x, // MRB continues
|
8'b10_10_01_10, // Clear (previously MR) and MRB needed
|
8'b10_10_01_10, // Clear (previously MR) and MRB needed
|
8'b01_1x_01_1x : // Clear (previously MW) and MRB needed
|
8'b01_1x_01_1x : // Clear (previously MW) and MRB needed
|
begin
|
begin
|
| Line 1060... |
Line 1164... |
tx_burst_cnt <= tx_burst_cnt+3'h1;
|
tx_burst_cnt <= tx_burst_cnt+3'h1;
|
if(tx_burst_cnt==0)
|
if(tx_burst_cnt==0)
|
m_wb_adr_o <= TxPointerMSB;
|
m_wb_adr_o <= TxPointerMSB;
|
else
|
else
|
m_wb_adr_o <= m_wb_adr_o+1'b1;
|
m_wb_adr_o <= m_wb_adr_o+1'b1;
|
|
|
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
|
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
|
begin
|
begin
|
tx_burst_en<= 1'b0;
|
tx_burst_en<= 1'b0;
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
m_wb_cti_o <= 3'b111;
|
m_wb_cti_o <= 3'b111;
|
| Line 1152... |
Line 1255... |
m_wb_we_o <= 1'b1;
|
m_wb_we_o <= 1'b1;
|
m_wb_sel_o <= RxByteSel;
|
m_wb_sel_o <= RxByteSel;
|
cyc_cleared<= 1'b0;
|
cyc_cleared<= 1'b0;
|
IncrTxPointer<= 1'b0;
|
IncrTxPointer<= 1'b0;
|
end
|
end
|
8'b01_01_10_00, // MW and MW needed (cycle is cleared between previous and next access)
|
8'b01_01_10_00,// MW and MW needed (cycle is cleared between
|
8'b01_1x_10_x0, // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
|
// previous and next access)
|
8'b10_10_10_00, // MR and MR needed (cycle is cleared between previous and next access)
|
8'b01_1x_10_x0,// MW and MW or MR or MRB needed (cycle is
|
8'b10_x1_10_0x : // MR and MR or MW or MWB (cycle is cleared between previous and next access)
|
// cleared between previous and next access)
|
begin
|
8'b10_10_10_00,// MR and MR needed (cycle is cleared between
|
m_wb_cyc_o <= 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
|
// previous and next access)
|
|
8'b10_x1_10_0x :// MR and MR or MW or MWB (cycle is cleared
|
|
// between previous and next access)
|
|
begin
|
|
m_wb_cyc_o <= 1'b0;// whatever and master read or write is
|
|
// needed. We need to clear m_wb_cyc_o
|
|
// before next access is started
|
cyc_cleared<= 1'b1;
|
cyc_cleared<= 1'b1;
|
IncrTxPointer<= 1'b0;
|
IncrTxPointer<= 1'b0;
|
tx_burst_cnt<= 0;
|
tx_burst_cnt<= 0;
|
tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
|
tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
|
rx_burst_cnt<= 0;
|
rx_burst_cnt<= 0;
|
rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
|
rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
m_wb_cti_o <= 3'b0;
|
m_wb_cti_o <= 3'b0;
|
`endif
|
`endif
|
end
|
end
|
8'bxx_00_10_00, // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
8'bxx_00_10_00,// whatever and no master read or write is needed
|
|
// (ack or err comes finishing previous access)
|
8'bxx_00_01_00 : // Between cyc_cleared request was cleared
|
8'bxx_00_01_00 : // Between cyc_cleared request was cleared
|
begin
|
begin
|
MasterWbTX <= 1'b0;
|
MasterWbTX <= 1'b0;
|
MasterWbRX <= 1'b0;
|
MasterWbRX <= 1'b0;
|
m_wb_cyc_o <= 1'b0;
|
m_wb_cyc_o <= 1'b0;
|
cyc_cleared<= 1'b0;
|
cyc_cleared<= 1'b0;
|
IncrTxPointer<= 1'b0;
|
IncrTxPointer<= 1'b0;
|
rx_burst_cnt<= 0;
|
rx_burst_cnt<= 0;
|
rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
|
// Counter is not decremented, yet, so plus1 is used.
|
|
rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 :
|
|
enough_data_in_rxfifo_for_burst;
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
m_wb_cti_o <= 3'b0;
|
m_wb_cti_o <= 3'b0;
|
`endif
|
`endif
|
end
|
end
|
8'b00_00_00_00: // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
8'b00_00_00_00: // whatever and no master read or write is needed
|
|
// (ack or err comes finishing previous access)
|
begin
|
begin
|
tx_burst_cnt<= 0;
|
tx_burst_cnt<= 0;
|
tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
|
tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
|
end
|
end
|
default: // Don't touch
|
default: // Don't touch
|
| Line 1199... |
Line 1312... |
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
wire TxFifoClear;
|
|
|
|
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
|
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
|
|
|
eth_fifo #(.DATA_WIDTH(TX_FIFO_DATA_WIDTH),
|
eth_fifo
|
|
#(
|
|
.DATA_WIDTH(TX_FIFO_DATA_WIDTH),
|
.DEPTH(TX_FIFO_DEPTH),
|
.DEPTH(TX_FIFO_DEPTH),
|
.CNT_WIDTH(TX_FIFO_CNT_WIDTH))
|
.CNT_WIDTH(TX_FIFO_CNT_WIDTH))
|
tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb),
|
tx_fifo (
|
.clk(WB_CLK_I), .reset(Reset),
|
.data_in(m_wb_dat_i),
|
.write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
|
.data_out(TxData_wb),
|
.clear(TxFifoClear), .full(TxBufferFull),
|
.clk(WB_CLK_I),
|
.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
|
.reset(Reset),
|
.empty(TxBufferEmpty), .cnt(txfifo_cnt)
|
.write(MasterWbTX & m_wb_ack_i),
|
|
.read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
|
|
.clear(TxFifoClear),
|
|
.full(TxBufferFull),
|
|
.almost_full(TxBufferAlmostFull),
|
|
.almost_empty(TxBufferAlmostEmpty),
|
|
.empty(TxBufferEmpty),
|
|
.cnt(txfifo_cnt)
|
);
|
);
|
|
|
|
// Start: Generation of the TxStartFrm_wb which is then synchronized to the
|
reg StartOccured;
|
// MTxClk
|
reg TxStartFrm_sync1;
|
|
reg TxStartFrm_sync2;
|
|
reg TxStartFrm_syncb1;
|
|
reg TxStartFrm_syncb2;
|
|
|
|
|
|
|
|
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxStartFrm_wb <= 1'b0;
|
TxStartFrm_wb <= 1'b0;
|
else
|
else
|
| Line 1237... |
Line 1348... |
else
|
else
|
if(TxStartFrm_syncb2)
|
if(TxStartFrm_syncb2)
|
TxStartFrm_wb <= 1'b0;
|
TxStartFrm_wb <= 1'b0;
|
end
|
end
|
|
|
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
|
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's
|
|
// blocked.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
StartOccured <= 1'b0;
|
StartOccured <= 1'b0;
|
else
|
else
|
| Line 1291... |
Line 1403... |
TxStartFrm <= 1'b0;
|
TxStartFrm <= 1'b0;
|
else
|
else
|
if(TxStartFrm_sync2)
|
if(TxStartFrm_sync2)
|
TxStartFrm <= 1'b1;
|
TxStartFrm <= 1'b1;
|
else
|
else
|
if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
|
if(TxUsedData_q | ~TxStartFrm_sync2 &
|
|
(TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
|
TxStartFrm <= 1'b0;
|
TxStartFrm <= 1'b0;
|
end
|
end
|
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
|
// End: Generation of the TxStartFrm_wb which is then synchronized to the
|
|
// MTxClk
|
|
|
|
|
// TxEndFrm_wb: indicator of the end of frame
|
// TxEndFrm_wb: indicator of the end of frame
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
| Line 1310... |
Line 1424... |
else
|
else
|
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
|
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
|
TxEndFrm_wb <= 1'b0;
|
TxEndFrm_wb <= 1'b0;
|
end
|
end
|
|
|
|
|
// Marks which bytes are valid within the word.
|
// Marks which bytes are valid within the word.
|
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
|
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
|
|
|
reg LatchValidBytes;
|
|
reg LatchValidBytes_q;
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
LatchValidBytes <= 1'b0;
|
LatchValidBytes <= 1'b0;
|
| Line 1362... |
Line 1473... |
assign RxIRQEn = RxStatus[14];
|
assign RxIRQEn = RxStatus[14];
|
assign WrapRxStatusBit = RxStatus[13];
|
assign WrapRxStatusBit = RxStatus[13];
|
|
|
|
|
// Temporary Tx and Rx buffer descriptor address
|
// Temporary Tx and Rx buffer descriptor address
|
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
|
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} &
|
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
|
(TxBDAddress + 1'b1); // Tx BD increment or wrap
|
{7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address)
|
// (last BD)
|
|
|
|
assign TempRxBDAddress[7:1] =
|
|
{7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
|
|
{7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1); // Using next Rx BD
|
|
// (increment address)
|
|
|
// Latching Tx buffer descriptor address
|
// Latching Tx buffer descriptor address
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 1378... |
Line 1493... |
TxBDAddress <= 7'h0;
|
TxBDAddress <= 7'h0;
|
else if (TxStatusWrite)
|
else if (TxStatusWrite)
|
TxBDAddress <= TempTxBDAddress;
|
TxBDAddress <= TempTxBDAddress;
|
end
|
end
|
|
|
|
|
// Latching Rx buffer descriptor address
|
// Latching Rx buffer descriptor address
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxBDAddress <= 7'h0;
|
RxBDAddress <= 7'h0;
|
| Line 1390... |
Line 1504... |
RxBDAddress <= r_TxBDNum[6:0];
|
RxBDAddress <= r_TxBDNum[6:0];
|
else if(RxStatusWrite)
|
else if(RxStatusWrite)
|
RxBDAddress <= TempRxBDAddress;
|
RxBDAddress <= TempRxBDAddress;
|
end
|
end
|
|
|
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
|
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0],
|
|
RetryLimit, LateCollLatched, DeferLatched,
|
|
CarrierSenseLost};
|
|
|
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
|
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
|
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
|
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
|
|
|
|
|
| Line 1402... |
Line 1518... |
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
|
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
|
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
|
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
|
assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
|
assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
|
|
|
|
|
|
|
// Generating delayed signals
|
// Generating delayed signals
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
| Line 1444... |
Line 1559... |
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxAbortPacket <= 1'b0;
|
TxAbortPacket <= 1'b0;
|
else
|
else
|
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
|
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
|
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
|
(~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
|
|
(~TxAbortPacketBlocked))
|
TxAbortPacket <= 1'b1;
|
TxAbortPacket <= 1'b1;
|
else
|
else
|
TxAbortPacket <= 1'b0;
|
TxAbortPacket <= 1'b0;
|
end
|
end
|
|
|
| Line 1460... |
Line 1576... |
TxAbortPacket_NotCleared <= 1'b0;
|
TxAbortPacket_NotCleared <= 1'b0;
|
else
|
else
|
if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
|
if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
|
TxAbortPacket_NotCleared <= 1'b0;
|
TxAbortPacket_NotCleared <= 1'b0;
|
else
|
else
|
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
|
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
|
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
|
(~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
|
|
(~TxAbortPacketBlocked))
|
TxAbortPacket_NotCleared <= 1'b1;
|
TxAbortPacket_NotCleared <= 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
| Line 1485... |
Line 1602... |
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxRetryPacket <= 1'b0;
|
TxRetryPacket <= 1'b0;
|
else
|
else
|
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
|
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
|
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
|
!TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
|
TxRetryPacket <= 1'b1;
|
TxRetryPacket <= 1'b1;
|
else
|
else
|
TxRetryPacket <= 1'b0;
|
TxRetryPacket <= 1'b0;
|
end
|
end
|
|
|
| Line 1501... |
Line 1618... |
TxRetryPacket_NotCleared <= 1'b0;
|
TxRetryPacket_NotCleared <= 1'b0;
|
else
|
else
|
if(StartTxBDRead)
|
if(StartTxBDRead)
|
TxRetryPacket_NotCleared <= 1'b0;
|
TxRetryPacket_NotCleared <= 1'b0;
|
else
|
else
|
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
|
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
|
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
|
!TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
|
TxRetryPacket_NotCleared <= 1'b1;
|
TxRetryPacket_NotCleared <= 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
| Line 1526... |
Line 1643... |
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxDonePacket <= 1'b0;
|
TxDonePacket <= 1'b0;
|
else
|
else
|
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
|
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
|
TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
|
!TxDonePacketBlocked | TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
|
TxDonePacket <= 1'b1;
|
TxDonePacket <= 1'b1;
|
else
|
else
|
TxDonePacket <= 1'b0;
|
TxDonePacket <= 1'b0;
|
end
|
end
|
|
|
| Line 1542... |
Line 1659... |
TxDonePacket_NotCleared <= 1'b0;
|
TxDonePacket_NotCleared <= 1'b0;
|
else
|
else
|
if(TxEn & TxEn_q & TxDonePacket_NotCleared)
|
if(TxEn & TxEn_q & TxDonePacket_NotCleared)
|
TxDonePacket_NotCleared <= 1'b0;
|
TxDonePacket_NotCleared <= 1'b0;
|
else
|
else
|
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) |
|
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
|
TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
|
(~TxDonePacketBlocked) | TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
|
TxDonePacket_NotCleared <= 1'b1;
|
TxDonePacket_NotCleared <= 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
| Line 1632... |
Line 1749... |
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxDataLatched[31:0] <= 32'h0;
|
TxDataLatched[31:0] <= 32'h0;
|
else
|
else
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 |
|
|
TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
|
TxDataLatched[31:0] <= TxData_wb[31:0];
|
TxDataLatched[31:0] <= TxData_wb[31:0];
|
end
|
end
|
|
|
|
|
// Tx under run
|
// Tx under run
|
| Line 1702... |
Line 1820... |
if(TxUsedData & Flop)
|
if(TxUsedData & Flop)
|
TxByteCnt <= TxByteCnt + 1'b1;
|
TxByteCnt <= TxByteCnt + 1'b1;
|
end
|
end
|
|
|
|
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
|
reg ReadTxDataFromFifo_sync1;
|
|
reg ReadTxDataFromFifo_sync2;
|
|
reg ReadTxDataFromFifo_sync3;
|
|
reg ReadTxDataFromFifo_syncb1;
|
|
reg ReadTxDataFromFifo_syncb2;
|
|
reg ReadTxDataFromFifo_syncb3;
|
|
|
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ReadTxDataFromFifo_tck <= 1'b0;
|
ReadTxDataFromFifo_tck <= 1'b0;
|
else
|
else
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 &
|
|
~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
|
ReadTxDataFromFifo_tck <= 1'b1;
|
ReadTxDataFromFifo_tck <= 1'b1;
|
else
|
else
|
if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
|
if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
|
ReadTxDataFromFifo_tck <= 1'b0;
|
ReadTxDataFromFifo_tck <= 1'b0;
|
end
|
end
|
| Line 1772... |
Line 1882... |
ReadTxDataFromFifo_sync3 <= 1'b0;
|
ReadTxDataFromFifo_sync3 <= 1'b0;
|
else
|
else
|
ReadTxDataFromFifo_sync3 <= ReadTxDataFromFifo_sync2;
|
ReadTxDataFromFifo_sync3 <= ReadTxDataFromFifo_sync2;
|
end
|
end
|
|
|
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
|
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 &
|
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
~ReadTxDataFromFifo_sync3;
|
|
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization
|
|
// to the WB_CLK_I
|
|
|
|
|
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
|
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
| Line 1829... |
Line 1941... |
else
|
else
|
TxAbort_wb <= TxAbortSync1;
|
TxAbort_wb <= TxAbortSync1;
|
end
|
end
|
|
|
|
|
reg RxAbortSync1;
|
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 |
|
reg RxAbortSync2;
|
r_RxEn & ~r_RxEn_q;
|
reg RxAbortSync3;
|
|
reg RxAbortSync4;
|
|
reg RxAbortSyncb1;
|
|
reg RxAbortSyncb2;
|
|
|
|
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 | r_RxEn & ~r_RxEn_q;
|
|
|
|
// Reading the Rx buffer descriptor
|
// Reading the Rx buffer descriptor
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 1852... |
Line 1958... |
if(RxBDReady)
|
if(RxBDReady)
|
RxBDRead <= 1'b0;
|
RxBDRead <= 1'b0;
|
end
|
end
|
|
|
|
|
// Reading of the next receive buffer descriptor starts after reception status is
|
// Reading of the next receive buffer descriptor starts after reception status
|
// written to the previous one.
|
// is written to the previous one.
|
|
|
// Latching READY status of the Rx buffer descriptor
|
// Latching READY status of the Rx buffer descriptor
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 1869... |
Line 1975... |
if(RxEn & RxEn_q & RxBDRead)
|
if(RxEn & RxEn_q & RxBDRead)
|
RxBDReady <= ram_do[15]; // RxBDReady is sampled only once at the beginning
|
RxBDReady <= ram_do[15]; // RxBDReady is sampled only once at the beginning
|
end
|
end
|
|
|
// Latching Rx buffer descriptor status
|
// Latching Rx buffer descriptor status
|
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
|
// Data is avaliable one cycle after the access is started (at that time
|
|
// signal RxEn is not active)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxStatus <= 2'h0;
|
RxStatus <= 2'h0;
|
else
|
else
|
| Line 1885... |
Line 1992... |
// RxReady generation
|
// RxReady generation
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxReady <= 1'b0;
|
RxReady <= 1'b0;
|
else
|
else if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
|
if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
|
|
RxReady <= 1'b0;
|
RxReady <= 1'b0;
|
else
|
else if(RxEn & RxEn_q & RxPointerRead)
|
if(RxEn & RxEn_q & RxPointerRead)
|
|
RxReady <= 1'b1;
|
RxReady <= 1'b1;
|
end
|
end
|
|
|
|
|
// Reading Rx BD pointer
|
// Reading Rx BD pointer
|
|
|
|
|
assign StartRxPointerRead = RxBDRead & RxBDReady;
|
assign StartRxPointerRead = RxBDRead & RxBDReady;
|
|
|
// Reading Tx BD Pointer
|
// Reading Tx BD Pointer
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
| Line 1923... |
Line 2026... |
else
|
else
|
if(RxEn & RxEn_q & RxPointerRead)
|
if(RxEn & RxEn_q & RxPointerRead)
|
RxPointerMSB <= ram_do[31:2];
|
RxPointerMSB <= ram_do[31:2];
|
else
|
else
|
if(MasterWbRX & m_wb_ack_i)
|
if(MasterWbRX & m_wb_ack_i)
|
RxPointerMSB <= RxPointerMSB + 1'b1; // Word access (always word access. m_wb_sel_o are used for selecting bytes)
|
RxPointerMSB <= RxPointerMSB + 1'b1; // Word access (always word access.
|
|
// m_wb_sel_o are used for
|
|
// selecting bytes)
|
end
|
end
|
|
|
|
|
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
|
//Latching last addresses from buffer descriptor (used as byte-half-word
|
|
//indicator);
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxPointerLSB_rst[1:0] <= 0;
|
RxPointerLSB_rst[1:0] <= 0;
|
else
|
else
|
| Line 1956... |
Line 2062... |
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxEn_needed <= 1'b0;
|
RxEn_needed <= 1'b0;
|
else
|
else if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
|
if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
|
|
RxEn_needed <= 1'b1;
|
RxEn_needed <= 1'b1;
|
else
|
else if(RxPointerRead & RxEn & RxEn_q)
|
if(RxPointerRead & RxEn & RxEn_q)
|
|
RxEn_needed <= 1'b0;
|
RxEn_needed <= 1'b0;
|
end
|
end
|
|
|
|
|
// Reception status is written back to the buffer descriptor after the end of frame is detected.
|
// Reception status is written back to the buffer descriptor after the end
|
|
// of frame is detected.
|
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
|
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
|
|
|
reg RxEnableWindow;
|
|
|
|
// Indicating that last byte is being reveived
|
// Indicating that last byte is being reveived
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 1983... |
Line 2087... |
else
|
else
|
if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
|
if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
|
LastByteIn <= 1'b1;
|
LastByteIn <= 1'b1;
|
end
|
end
|
|
|
reg ShiftEnded_rck;
|
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) &
|
reg ShiftEndedSync1;
|
RxEnableWindow;
|
reg ShiftEndedSync2;
|
|
reg ShiftEndedSync3;
|
|
reg ShiftEndedSync_c1;
|
|
reg ShiftEndedSync_c2;
|
|
|
|
wire StartShiftWillEnd;
|
|
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
|
|
|
|
// Indicating that data reception will end
|
// Indicating that data reception will end
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 2007... |
Line 2104... |
if(StartShiftWillEnd)
|
if(StartShiftWillEnd)
|
ShiftWillEnd <= 1'b1;
|
ShiftWillEnd <= 1'b1;
|
end
|
end
|
|
|
|
|
|
|
// Receive byte counter
|
// Receive byte counter
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxByteCnt <= 2'h0;
|
RxByteCnt <= 2'h0;
|
| Line 2058... |
Line 2154... |
else
|
else
|
if(RxValid & RxReady & ~LastByteIn)
|
if(RxValid & RxReady & ~LastByteIn)
|
if(RxStartFrm)
|
if(RxStartFrm)
|
begin
|
begin
|
case(RxPointerLSB_rst) // synopsys parallel_case
|
case(RxPointerLSB_rst) // synopsys parallel_case
|
2'h0: RxDataLatched1[31:24] <= RxData; // Big Endian Byte Ordering
|
// Big Endian Byte Ordering
|
|
2'h0: RxDataLatched1[31:24] <= RxData;
|
2'h1: RxDataLatched1[23:16] <= RxData;
|
2'h1: RxDataLatched1[23:16] <= RxData;
|
2'h2: RxDataLatched1[15:8] <= RxData;
|
2'h2: RxDataLatched1[15:8] <= RxData;
|
2'h3: RxDataLatched1 <= RxDataLatched1;
|
2'h3: RxDataLatched1 <= RxDataLatched1;
|
endcase
|
endcase
|
end
|
end
|
else if (RxEnableWindow)
|
else if (RxEnableWindow)
|
begin
|
begin
|
case(RxByteCnt) // synopsys parallel_case
|
case(RxByteCnt) // synopsys parallel_case
|
2'h0: RxDataLatched1[31:24] <= RxData; // Big Endian Byte Ordering
|
// Big Endian Byte Ordering
|
|
2'h0: RxDataLatched1[31:24] <= RxData;
|
2'h1: RxDataLatched1[23:16] <= RxData;
|
2'h1: RxDataLatched1[23:16] <= RxData;
|
2'h2: RxDataLatched1[15:8] <= RxData;
|
2'h2: RxDataLatched1[15:8] <= RxData;
|
2'h3: RxDataLatched1 <= RxDataLatched1;
|
2'h3: RxDataLatched1 <= RxDataLatched1;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
wire SetWriteRxDataToFifo;
|
|
|
|
// Assembling data that will be written to the rx_fifo
|
// Assembling data that will be written to the rx_fifo
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxDataLatched2 <= 32'h0;
|
RxDataLatched2 <= 32'h0;
|
else
|
else
|
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
|
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
|
RxDataLatched2 <= {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
// Big Endian Byte Ordering
|
|
RxDataLatched2 <= {RxDataLatched1[31:8], RxData};
|
else
|
else
|
if(SetWriteRxDataToFifo & ShiftWillEnd)
|
if(SetWriteRxDataToFifo & ShiftWillEnd)
|
case(RxValidBytes) // synopsys parallel_case
|
case(RxValidBytes) // synopsys parallel_case
|
0 : RxDataLatched2 <= {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
// Big Endian Byte Ordering
|
|
0 : RxDataLatched2 <= {RxDataLatched1[31:8], RxData};
|
1 : RxDataLatched2 <= {RxDataLatched1[31:24], 24'h0};
|
1 : RxDataLatched2 <= {RxDataLatched1[31:24], 24'h0};
|
2 : RxDataLatched2 <= {RxDataLatched1[31:16], 16'h0};
|
2 : RxDataLatched2 <= {RxDataLatched1[31:16], 16'h0};
|
3 : RxDataLatched2 <= {RxDataLatched1[31:8], 8'h0};
|
3 : RxDataLatched2 <= {RxDataLatched1[31:8], 8'h0};
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
reg WriteRxDataToFifoSync1;
|
|
reg WriteRxDataToFifoSync2;
|
|
reg WriteRxDataToFifoSync3;
|
|
|
|
|
|
// Indicating start of the reception process
|
// Indicating start of the reception process
|
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
|
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm &
|
(RxValid & RxReady & RxStartFrm & (&RxPointerLSB_rst)) |
|
RxEnableWindow & (&RxByteCnt))
|
(ShiftWillEnd & LastByteIn & (&RxByteCnt));
|
|(RxValid & RxReady & RxStartFrm &
|
|
(&RxPointerLSB_rst))
|
|
|(ShiftWillEnd & LastByteIn & (&RxByteCnt));
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
WriteRxDataToFifo <= 1'b0;
|
WriteRxDataToFifo <= 1'b0;
|
| Line 2119... |
Line 2214... |
if(WriteRxDataToFifoSync2 | RxAbort)
|
if(WriteRxDataToFifoSync2 | RxAbort)
|
WriteRxDataToFifo <= 1'b0;
|
WriteRxDataToFifo <= 1'b0;
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
WriteRxDataToFifoSync1 <= 1'b0;
|
WriteRxDataToFifoSync1 <= 1'b0;
|
else
|
else
|
| Line 2147... |
Line 2241... |
WriteRxDataToFifoSync3 <= 1'b0;
|
WriteRxDataToFifoSync3 <= 1'b0;
|
else
|
else
|
WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2;
|
WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2;
|
end
|
end
|
|
|
wire WriteRxDataToFifo_wb;
|
|
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
|
|
|
|
|
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 &
|
|
~WriteRxDataToFifoSync3;
|
|
|
reg LatchedRxStartFrm;
|
|
reg SyncRxStartFrm;
|
|
reg SyncRxStartFrm_q;
|
|
reg SyncRxStartFrm_q2;
|
|
wire RxFifoReset;
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
LatchedRxStartFrm <= 0;
|
LatchedRxStartFrm <= 0;
|
| Line 2201... |
Line 2290... |
end
|
end
|
|
|
|
|
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
|
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
|
|
|
eth_fifo #(.DATA_WIDTH(RX_FIFO_DATA_WIDTH),
|
eth_fifo #(
|
|
.DATA_WIDTH(RX_FIFO_DATA_WIDTH),
|
.DEPTH(RX_FIFO_DEPTH),
|
.DEPTH(RX_FIFO_DEPTH),
|
.CNT_WIDTH(RX_FIFO_CNT_WIDTH))
|
.CNT_WIDTH(RX_FIFO_CNT_WIDTH))
|
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
|
rx_fifo (
|
.clk(WB_CLK_I), .reset(Reset),
|
.clk (WB_CLK_I),
|
.write(WriteRxDataToFifo_wb & ~RxBufferFull), .read(MasterWbRX & m_wb_ack_i),
|
.reset (Reset),
|
.clear(RxFifoReset), .full(RxBufferFull),
|
// Inputs
|
.almost_full(), .almost_empty(RxBufferAlmostEmpty),
|
.data_in (RxDataLatched2),
|
.empty(RxBufferEmpty), .cnt(rxfifo_cnt)
|
.write (WriteRxDataToFifo_wb & ~RxBufferFull),
|
|
.read (MasterWbRX & m_wb_ack_i),
|
|
.clear (RxFifoReset),
|
|
// Outputs
|
|
.data_out (m_wb_dat_o),
|
|
.full (RxBufferFull),
|
|
.almost_full (),
|
|
.almost_empty (RxBufferAlmostEmpty),
|
|
.empty (RxBufferEmpty),
|
|
.cnt (rxfifo_cnt)
|
);
|
);
|
|
|
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
|
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
|
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
|
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
|
assign WriteRxDataToMemory = ~RxBufferEmpty;
|
assign WriteRxDataToMemory = ~RxBufferEmpty;
|
| Line 2293... |
Line 2392... |
// Generation of the end-of-frame signal
|
// Generation of the end-of-frame signal
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxEnableWindow <= 1'b0;
|
RxEnableWindow <= 1'b0;
|
else
|
else if(RxStartFrm)
|
if(RxStartFrm)
|
|
RxEnableWindow <= 1'b1;
|
RxEnableWindow <= 1'b1;
|
else
|
else if(RxEndFrm | RxAbort)
|
if(RxEndFrm | RxAbort)
|
|
RxEnableWindow <= 1'b0;
|
RxEnableWindow <= 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
| Line 2374... |
Line 2471... |
if(LoadRxStatus)
|
if(LoadRxStatus)
|
LatchedRxLength[15:0] <= RxLength[15:0];
|
LatchedRxLength[15:0] <= RxLength[15:0];
|
end
|
end
|
|
|
|
|
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
|
assign RxStatusIn = {ReceivedPauseFrm,
|
|
AddressMiss,
|
|
RxOverrun,
|
|
InvalidSymbol,
|
|
DribbleNibble,
|
|
ReceivedPacketTooBig,
|
|
ShortFrame,
|
|
LatchedCrcError,
|
|
RxLateCollision};
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxStatusInLatched <= 'h0;
|
RxStatusInLatched <= 'h0;
|
| Line 2391... |
Line 2496... |
// Rx overrun
|
// Rx overrun
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxOverrun <= 1'b0;
|
RxOverrun <= 1'b0;
|
else
|
else if(RxStatusWrite)
|
if(RxStatusWrite)
|
|
RxOverrun <= 1'b0;
|
RxOverrun <= 1'b0;
|
else
|
else if(RxBufferFull & WriteRxDataToFifo_wb)
|
if(RxBufferFull & WriteRxDataToFifo_wb)
|
|
RxOverrun <= 1'b1;
|
RxOverrun <= 1'b1;
|
end
|
end
|
|
|
|
|
|
|
wire TxError;
|
|
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
|
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
|
|
|
wire RxError;
|
|
|
|
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
|
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
|
// are aborted when signal r_RecSmall is set to 0 in MODER register.
|
// are aborted when signal r_RecSmall is set to 0 in MODER register.
|
// AddressMiss is identifying that a frame was received because of the promiscous
|
// AddressMiss is identifying that a frame was received because of the
|
// mode and is not an error
|
// promiscous mode and is not an error
|
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
|
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
|
|
|
|
|
|
// Latching and synchronizing RxStatusWrite signal. This signal is used for
|
reg RxStatusWriteLatched;
|
// clearing the ReceivedPauseFrm signal
|
reg RxStatusWriteLatched_sync1;
|
|
reg RxStatusWriteLatched_sync2;
|
|
reg RxStatusWriteLatched_syncb1;
|
|
reg RxStatusWriteLatched_syncb2;
|
|
|
|
|
|
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxStatusWriteLatched <= 1'b0;
|
RxStatusWriteLatched <= 1'b0;
|
else
|
else
|
| Line 2465... |
Line 2558... |
RxStatusWriteLatched_syncb2 <= RxStatusWriteLatched_syncb1;
|
RxStatusWriteLatched_syncb2 <= RxStatusWriteLatched_syncb1;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
// Tx Done Interrupt
|
// Tx Done Interrupt
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxB_IRQ <= 1'b0;
|
TxB_IRQ <= 1'b0;
|
| Line 2498... |
Line 2590... |
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxB_IRQ <= 1'b0;
|
RxB_IRQ <= 1'b0;
|
else
|
else
|
if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
|
if(RxStatusWrite & RxIRQEn & ReceivedPacketGood &
|
|
(~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
|
RxB_IRQ <= (~RxError);
|
RxB_IRQ <= (~RxError);
|
else
|
else
|
RxB_IRQ <= 1'b0;
|
RxB_IRQ <= 1'b0;
|
end
|
end
|
|
|
| Line 2511... |
Line 2604... |
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxE_IRQ <= 1'b0;
|
RxE_IRQ <= 1'b0;
|
else
|
else
|
if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
|
if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm
|
|
& r_PassAll & (~r_RxFlow)))
|
RxE_IRQ <= RxError;
|
RxE_IRQ <= RxError;
|
else
|
else
|
RxE_IRQ <= 1'b0;
|
RxE_IRQ <= 1'b0;
|
end
|
end
|
|
|
