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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 354 and 355

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Rev 354 Rev 355
Line 747... Line 747...
      BDWrite <= 1'b0;
      BDWrite <= 1'b0;
    end
    end
  else
  else
    begin
    begin
      // Switching between three stages depends on enable signals
      // Switching between three stages depends on enable signals
 
     /* verilator lint_off CASEINCOMPLETE */ // JB
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
        5'b100_10, 5'b100_11 :
        5'b100_10, 5'b100_11 :
          begin
          begin
            WbEn <= 1'b0;
            WbEn <= 1'b0;
            RxEn <= 1'b1;  // wb access stage and r_RxEn is enabled
            RxEn <= 1'b1;  // wb access stage and r_RxEn is enabled
Line 811... Line 812...
            ram_di <= WB_DAT_I;
            ram_di <= WB_DAT_I;
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
            BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
            BDRead <= (|BDCs) & ~WB_WE_I;
            BDRead <= (|BDCs) & ~WB_WE_I;
          end
          end
      endcase
      endcase
 
      /* verilator lint_on CASEINCOMPLETE */
    end
    end
end
end
 
 
 
 
// Delayed stage signals
// Delayed stage signals

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