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https://opencores.org/ocsvn/ethmac/ethmac/trunk
[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Diff between revs 354 and 355
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| Rev 354 |
Rev 355 |
| Line 747... |
Line 747... |
BDWrite <= 1'b0;
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BDWrite <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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// Switching between three stages depends on enable signals
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// Switching between three stages depends on enable signals
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/* verilator lint_off CASEINCOMPLETE */ // JB
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case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
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case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
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5'b100_10, 5'b100_11 :
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5'b100_10, 5'b100_11 :
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begin
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begin
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WbEn <= 1'b0;
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WbEn <= 1'b0;
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RxEn <= 1'b1; // wb access stage and r_RxEn is enabled
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RxEn <= 1'b1; // wb access stage and r_RxEn is enabled
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| Line 811... |
Line 812... |
ram_di <= WB_DAT_I;
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ram_di <= WB_DAT_I;
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BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
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BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
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BDRead <= (|BDCs) & ~WB_WE_I;
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BDRead <= (|BDCs) & ~WB_WE_I;
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end
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end
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endcase
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endcase
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/* verilator lint_on CASEINCOMPLETE */
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end
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end
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end
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end
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// Delayed stage signals
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// Delayed stage signals
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