| Line 742... |
Line 742... |
RxEn <= 1'b0;
|
RxEn <= 1'b0;
|
TxEn <= 1'b0;
|
TxEn <= 1'b0;
|
ram_addr <= 8'h0;
|
ram_addr <= 8'h0;
|
ram_di <= 32'h0;
|
ram_di <= 32'h0;
|
BDRead <= 1'b0;
|
BDRead <= 1'b0;
|
BDWrite <= 1'b0;
|
BDWrite <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// Switching between three stages depends on enable signals
|
// Switching between three stages depends on enable signals
|
/* verilator lint_off CASEINCOMPLETE */ // JB
|
/* verilator lint_off CASEINCOMPLETE */ // JB
|
| Line 992... |
Line 992... |
if(MasterWbTX & m_wb_ack_i)
|
if(MasterWbTX & m_wb_ack_i)
|
begin
|
begin
|
if(TxLengthLt4)
|
if(TxLengthLt4)
|
TxLength <= 16'h0;
|
TxLength <= 16'h0;
|
else if(TxPointerLSB_rst==2'h0)
|
else if(TxPointerLSB_rst==2'h0)
|
TxLength <= TxLength - 3'h4; // Length is subtracted at
|
TxLength <= TxLength - 16'd4; // Length is subtracted at
|
// the data request
|
// the data request
|
else if(TxPointerLSB_rst==2'h1)
|
else if(TxPointerLSB_rst==2'h1)
|
TxLength <= TxLength - 3'h3; // Length is subtracted
|
TxLength <= TxLength - 16'd3; // Length is subtracted
|
// at the data request
|
// at the data request
|
else if(TxPointerLSB_rst==2'h2)
|
else if(TxPointerLSB_rst==2'h2)
|
TxLength <= TxLength - 3'h2; // Length is subtracted
|
TxLength <= TxLength - 16'd2; // Length is subtracted
|
// at the data request
|
// at the data request
|
else if(TxPointerLSB_rst==2'h3)
|
else if(TxPointerLSB_rst==2'h3)
|
TxLength <= TxLength - 3'h1; // Length is subtracted
|
TxLength <= TxLength - 16'd1; // Length is subtracted
|
// at the data request
|
// at the data request
|
end
|
end
|
end
|
end
|
|
|
//Latching length from the buffer descriptor;
|
//Latching length from the buffer descriptor;
|
| Line 1140... |
Line 1140... |
`endif
|
`endif
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// Switching between two stages depends on enable signals
|
// Switching between two stages depends on enable signals
|
casex ({MasterWbTX,
|
casez ({MasterWbTX,
|
MasterWbRX,
|
MasterWbRX,
|
ReadTxDataFromMemory_2,
|
ReadTxDataFromMemory_2,
|
WriteRxDataToMemory,
|
WriteRxDataToMemory,
|
MasterAccessFinished,
|
MasterAccessFinished,
|
cyc_cleared,
|
cyc_cleared,
|
tx_burst,
|
tx_burst,
|
rx_burst}) // synopsys parallel_case
|
rx_burst}) // synopsys parallel_case
|
|
|
8'b00_10_00_10, // Idle and MRB needed
|
8'b00_10_00_10, // Idle and MRB needed
|
8'b10_1x_10_1x, // MRB continues
|
8'b10_1?_10_1?, // MRB continues
|
8'b10_10_01_10, // Clear (previously MR) and MRB needed
|
8'b10_10_01_10, // Clear (previously MR) and MRB needed
|
8'b01_1x_01_1x :// Clear (previously MW) and MRB needed
|
8'b01_1?_01_1?: // Clear (previously MW) and MRB needed
|
begin
|
begin
|
MasterWbTX <= 1'b1; // tx burst
|
MasterWbTX <= 1'b1; // tx burst
|
MasterWbRX <= 1'b0;
|
MasterWbRX <= 1'b0;
|
m_wb_cyc_o <= 1'b1;
|
m_wb_cyc_o <= 1'b1;
|
m_wb_we_o <= 1'b0;
|
m_wb_we_o <= 1'b0;
|
| Line 1180... |
Line 1180... |
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
m_wb_cti_o <= 3'b010;
|
m_wb_cti_o <= 3'b010;
|
`endif
|
`endif
|
end
|
end
|
end
|
end
|
8'b00_x1_00_x1, // Idle and MWB needed
|
8'b00_?1_00_?1, // Idle and MWB needed
|
8'b01_x1_10_x1, // MWB continues
|
8'b01_?1_10_?1, // MWB continues
|
8'b01_01_01_01, // Clear (previously MW) and MWB needed
|
8'b01_01_01_01, // Clear (previously MW) and MWB needed
|
8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed
|
8'b10_?1_01_?1 : // Clear (previously MR) and MWB needed
|
begin
|
begin
|
MasterWbTX <= 1'b0; // rx burst
|
MasterWbTX <= 1'b0; // rx burst
|
MasterWbRX <= 1'b1;
|
MasterWbRX <= 1'b1;
|
m_wb_cyc_o <= 1'b1;
|
m_wb_cyc_o <= 1'b1;
|
m_wb_we_o <= 1'b1;
|
m_wb_we_o <= 1'b1;
|
| Line 1213... |
Line 1213... |
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
m_wb_cti_o <= 3'b010;
|
m_wb_cti_o <= 3'b010;
|
`endif
|
`endif
|
end
|
end
|
end
|
end
|
8'b00_x1_00_x0 :// idle and MW is needed (data write to rx buffer)
|
8'b00_?1_00_?0 :// idle and MW is needed (data write to rx buffer)
|
begin
|
begin
|
MasterWbTX <= 1'b0;
|
MasterWbTX <= 1'b0;
|
MasterWbRX <= 1'b1;
|
MasterWbRX <= 1'b1;
|
m_wb_adr_o <= RxPointerMSB;
|
m_wb_adr_o <= RxPointerMSB;
|
m_wb_cyc_o <= 1'b1;
|
m_wb_cyc_o <= 1'b1;
|
| Line 1234... |
Line 1234... |
m_wb_we_o <= 1'b0;
|
m_wb_we_o <= 1'b0;
|
m_wb_sel_o <= 4'hf;
|
m_wb_sel_o <= 4'hf;
|
IncrTxPointer<= 1'b1;
|
IncrTxPointer<= 1'b1;
|
end
|
end
|
8'b10_10_01_00,// MR and MR is needed (data read from tx buffer)
|
8'b10_10_01_00,// MR and MR is needed (data read from tx buffer)
|
8'b01_1x_01_0x :// MW and MR is needed (data read from tx buffer)
|
8'b01_1?_01_0? :// MW and MR is needed (data read from tx buffer)
|
begin
|
begin
|
MasterWbTX <= 1'b1;
|
MasterWbTX <= 1'b1;
|
MasterWbRX <= 1'b0;
|
MasterWbRX <= 1'b0;
|
m_wb_adr_o <= TxPointerMSB;
|
m_wb_adr_o <= TxPointerMSB;
|
m_wb_cyc_o <= 1'b1;
|
m_wb_cyc_o <= 1'b1;
|
| Line 1246... |
Line 1246... |
m_wb_sel_o <= 4'hf;
|
m_wb_sel_o <= 4'hf;
|
cyc_cleared<= 1'b0;
|
cyc_cleared<= 1'b0;
|
IncrTxPointer<= 1'b1;
|
IncrTxPointer<= 1'b1;
|
end
|
end
|
8'b01_01_01_00,// MW and MW needed (data write to rx buffer)
|
8'b01_01_01_00,// MW and MW needed (data write to rx buffer)
|
8'b10_x1_01_x0 :// MR and MW is needed (data write to rx buffer)
|
8'b10_?1_01_?0 :// MR and MW is needed (data write to rx buffer)
|
begin
|
begin
|
MasterWbTX <= 1'b0;
|
MasterWbTX <= 1'b0;
|
MasterWbRX <= 1'b1;
|
MasterWbRX <= 1'b1;
|
m_wb_adr_o <= RxPointerMSB;
|
m_wb_adr_o <= RxPointerMSB;
|
m_wb_cyc_o <= 1'b1;
|
m_wb_cyc_o <= 1'b1;
|
| Line 1259... |
Line 1259... |
cyc_cleared<= 1'b0;
|
cyc_cleared<= 1'b0;
|
IncrTxPointer<= 1'b0;
|
IncrTxPointer<= 1'b0;
|
end
|
end
|
8'b01_01_10_00,// MW and MW needed (cycle is cleared between
|
8'b01_01_10_00,// MW and MW needed (cycle is cleared between
|
// previous and next access)
|
// previous and next access)
|
8'b01_1x_10_x0,// MW and MW or MR or MRB needed (cycle is
|
8'b01_1?_10_?0,// MW and MW or MR or MRB needed (cycle is
|
// cleared between previous and next access)
|
// cleared between previous and next access)
|
8'b10_10_10_00,// MR and MR needed (cycle is cleared between
|
8'b10_10_10_00,// MR and MR needed (cycle is cleared between
|
// previous and next access)
|
// previous and next access)
|
8'b10_x1_10_0x :// MR and MR or MW or MWB (cycle is cleared
|
8'b10_?1_10_0? :// MR and MR or MW or MWB (cycle is cleared
|
// between previous and next access)
|
// between previous and next access)
|
begin
|
begin
|
m_wb_cyc_o <= 1'b0;// whatever and master read or write is
|
m_wb_cyc_o <= 1'b0;// whatever and master read or write is
|
// needed. We need to clear m_wb_cyc_o
|
// needed. We need to clear m_wb_cyc_o
|
// before next access is started
|
// before next access is started
|
| Line 1279... |
Line 1279... |
rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
|
rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
m_wb_cti_o <= 3'b0;
|
m_wb_cti_o <= 3'b0;
|
`endif
|
`endif
|
end
|
end
|
8'bxx_00_10_00,// whatever and no master read or write is needed
|
8'b??_00_10_00,// whatever and no master read or write is needed
|
// (ack or err comes finishing previous access)
|
// (ack or err comes finishing previous access)
|
8'bxx_00_01_00 : // Between cyc_cleared request was cleared
|
8'b??_00_01_00 : // Between cyc_cleared request was cleared
|
begin
|
begin
|
MasterWbTX <= 1'b0;
|
MasterWbTX <= 1'b0;
|
MasterWbRX <= 1'b0;
|
MasterWbRX <= 1'b0;
|
m_wb_cyc_o <= 1'b0;
|
m_wb_cyc_o <= 1'b0;
|
cyc_cleared<= 1'b0;
|
cyc_cleared<= 1'b0;
|
