| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.13 2002/02/26 16:59:55 mohor
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// Small fixes for external/internal DMA missmatches.
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//
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// Revision 1.12 2002/02/26 16:22:07 mohor
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// Revision 1.12 2002/02/26 16:22:07 mohor
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// Interrupts changed
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// Interrupts changed
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//
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//
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// Revision 1.11 2002/02/15 17:07:39 mohor
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// Revision 1.11 2002/02/15 17:07:39 mohor
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// Status was not written correctly when frames were discarted because of
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// Status was not written correctly when frames were discarted because of
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| Line 131... |
Line 134... |
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
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InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
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ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
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ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
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// Tx Status
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// Tx Status
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RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
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RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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| Line 281... |
Line 283... |
reg TxAbort_q;
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reg TxAbort_q;
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reg TxRetry_q;
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reg TxRetry_q;
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reg TxUsedData_q;
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reg TxUsedData_q;
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reg [31:0] RxDataLatched2;
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reg [31:0] RxDataLatched2;
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reg [23:0] RxDataLatched1;
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// reg [23:0] RxDataLatched1;
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reg [31:8] RxDataLatched1; // Big Endian Byte Ordering
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reg [1:0] RxValidBytes;
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reg [1:0] RxValidBytes;
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reg [1:0] RxByteCnt;
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reg [1:0] RxByteCnt;
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reg LastByteIn;
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reg LastByteIn;
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reg ShiftWillEnd;
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reg ShiftWillEnd;
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| Line 765... |
Line 770... |
m_wb_we_o <=#Tp 1'b0;
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m_wb_we_o <=#Tp 1'b0;
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end
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end
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else
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else
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begin
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begin
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// Switching between two stages depends on enable signals
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// Switching between two stages depends on enable signals
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casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished}) // synopsys parallel_case full_case
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case ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished})
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5'b00_x1_x :
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5'b00_01_0, 5'b00_11_0 :
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begin
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begin
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MasterWbTX <=#Tp 1'b0; // idle and master write is needed (data write to rx buffer)
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MasterWbTX <=#Tp 1'b0; // idle and master write is needed (data write to rx buffer)
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MasterWbRX <=#Tp 1'b1;
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MasterWbRX <=#Tp 1'b1;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_cyc_o <=#Tp 1'b1;
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m_wb_cyc_o <=#Tp 1'b1;
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m_wb_stb_o <=#Tp 1'b1;
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m_wb_stb_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b1;
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end
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end
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5'b00_10_x :
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5'b00_10_0, 5'b00_10_1 :
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begin
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begin
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MasterWbTX <=#Tp 1'b1; // idle and master read is needed (data read from tx buffer)
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MasterWbTX <=#Tp 1'b1; // idle and master read is needed (data read from tx buffer)
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MasterWbRX <=#Tp 1'b0;
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MasterWbRX <=#Tp 1'b0;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_cyc_o <=#Tp 1'b1;
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m_wb_cyc_o <=#Tp 1'b1;
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| Line 800... |
Line 805... |
MasterWbTX <=#Tp 1'b0; // master write and master write is needed (data write to rx buffer)
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MasterWbTX <=#Tp 1'b0; // master write and master write is needed (data write to rx buffer)
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MasterWbRX <=#Tp 1'b1;
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MasterWbRX <=#Tp 1'b1;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_we_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b1;
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end
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end
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5'b10_x1_1 :
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5'b10_01_1, 5'b10_11_1 :
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begin
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begin
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MasterWbTX <=#Tp 1'b0; // master read and master write is needed (data write to rx buffer)
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MasterWbTX <=#Tp 1'b0; // master read and master write is needed (data write to rx buffer)
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MasterWbRX <=#Tp 1'b1;
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MasterWbRX <=#Tp 1'b1;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_we_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b1;
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end
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end
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5'b01_1x_1 :
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5'b01_10_1, 5'b01_11_1 :
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begin
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begin
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MasterWbTX <=#Tp 1'b1; // master write and master read is needed (data read from tx buffer)
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MasterWbTX <=#Tp 1'b1; // master write and master read is needed (data read from tx buffer)
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MasterWbRX <=#Tp 1'b0;
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MasterWbRX <=#Tp 1'b0;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_we_o <=#Tp 1'b0;
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m_wb_we_o <=#Tp 1'b0;
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end
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end
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5'bxx_00_1 :
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5'b10_00_1, 5'b01_00_1 :
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begin
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begin
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MasterWbTX <=#Tp 1'b0; // whatever and no master read or write is needed (ack or err comes finishing previous access)
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MasterWbTX <=#Tp 1'b0; // whatever and no master read or write is needed (ack or err comes finishing previous access)
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MasterWbRX <=#Tp 1'b0;
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MasterWbRX <=#Tp 1'b0;
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m_wb_cyc_o <=#Tp 1'b0;
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m_wb_cyc_o <=#Tp 1'b0;
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m_wb_stb_o <=#Tp 1'b0;
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m_wb_stb_o <=#Tp 1'b0;
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end
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end
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default: // Don't touch
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begin
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MasterWbTX <=#Tp MasterWbTX;
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MasterWbRX <=#Tp MasterWbRX;
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m_wb_cyc_o <=#Tp m_wb_cyc_o;
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m_wb_stb_o <=#Tp m_wb_stb_o;
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end
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endcase
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endcase
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end
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end
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end
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end
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wire TxFifoClear;
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wire TxFifoClear;
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| Line 1120... |
Line 1132... |
TxData <=#Tp TxData_wb[7:0];
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TxData <=#Tp TxData_wb[7:0];
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else
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else
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if(TxUsedData & Flop)
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if(TxUsedData & Flop)
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begin
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begin
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case(TxByteCnt)
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case(TxByteCnt)
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0 : TxData <=#Tp TxDataLatched[7:0];
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// 0 : TxData <=#Tp TxDataLatched[7:0];
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1 : TxData <=#Tp TxDataLatched[15:8];
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// 1 : TxData <=#Tp TxDataLatched[15:8];
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2 : TxData <=#Tp TxDataLatched[23:16];
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// 2 : TxData <=#Tp TxDataLatched[23:16];
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3 : TxData <=#Tp TxDataLatched[31:24];
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// 3 : TxData <=#Tp TxDataLatched[31:24];
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0 : TxData <=#Tp TxDataLatched[31:24]; // Big Endian Byte Ordering
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1 : TxData <=#Tp TxDataLatched[23:16];
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2 : TxData <=#Tp TxDataLatched[15:8];
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3 : TxData <=#Tp TxDataLatched[7:0];
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endcase
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endcase
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end
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end
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end
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end
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| Line 1509... |
Line 1525... |
RxDataLatched1 <=#Tp 24'h0;
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RxDataLatched1 <=#Tp 24'h0;
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else
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else
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if(RxValid & RxBDReady & ~LastByteIn & (RxStartFrm | RxEnableWindow))
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if(RxValid & RxBDReady & ~LastByteIn & (RxStartFrm | RxEnableWindow))
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begin
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begin
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case(RxByteCnt) // synopsys parallel_case
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case(RxByteCnt) // synopsys parallel_case
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2'h0: RxDataLatched1[7:0] <=#Tp RxData;
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// 2'h0: RxDataLatched1[7:0] <=#Tp RxData;
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2'h1: RxDataLatched1[15:8] <=#Tp RxData;
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// 2'h1: RxDataLatched1[15:8] <=#Tp RxData;
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2'h2: RxDataLatched1[23:16] <=#Tp RxData;
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// 2'h2: RxDataLatched1[23:16] <=#Tp RxData;
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// 2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
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2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
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2'h1: RxDataLatched1[23:16] <=#Tp RxData;
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2'h2: RxDataLatched1[15:8] <=#Tp RxData;
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2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
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2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
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endcase
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endcase
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end
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end
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end
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end
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| Line 1526... |
Line 1546... |
begin
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begin
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if(Reset)
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if(Reset)
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RxDataLatched2 <=#Tp 32'h0;
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RxDataLatched2 <=#Tp 32'h0;
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else
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else
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if(SetWriteRxDataToFifo & ~ShiftWillEnd)
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if(SetWriteRxDataToFifo & ~ShiftWillEnd)
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RxDataLatched2 <=#Tp {RxData, RxDataLatched1[23:0]};
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// RxDataLatched2 <=#Tp {RxData, RxDataLatched1[23:0]};
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RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
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else
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else
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if(SetWriteRxDataToFifo & ShiftWillEnd)
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if(SetWriteRxDataToFifo & ShiftWillEnd)
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case(RxValidBytes)
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case(RxValidBytes)
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0 : RxDataLatched2 <=#Tp {RxData, RxDataLatched1[23:0]};
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// 0 : RxDataLatched2 <=#Tp {RxData, RxDataLatched1[23:0]};
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1 : RxDataLatched2 <=#Tp { 24'h0, RxDataLatched1[7:0]};
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// 1 : RxDataLatched2 <=#Tp { 24'h0, RxDataLatched1[7:0]};
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2 : RxDataLatched2 <=#Tp { 16'h0, RxDataLatched1[15:0]};
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// 2 : RxDataLatched2 <=#Tp { 16'h0, RxDataLatched1[15:0]};
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3 : RxDataLatched2 <=#Tp { 8'h0, RxDataLatched1[23:0]};
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// 3 : RxDataLatched2 <=#Tp { 8'h0, RxDataLatched1[23:0]};
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0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
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1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
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2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
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3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0};
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endcase
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endcase
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end
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end
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reg WriteRxDataToFifoSync1;
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reg WriteRxDataToFifoSync1;
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