| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.18 2002/03/19 12:46:52 mohor
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// casex changed with case, fifo reset changed.
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//
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// Revision 1.17 2002/03/09 16:08:45 mohor
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// Revision 1.17 2002/03/09 16:08:45 mohor
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// rx_fifo was not always cleared ok. Fixed.
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// rx_fifo was not always cleared ok. Fixed.
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//
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//
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// Revision 1.16 2002/03/09 13:51:20 mohor
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// Revision 1.16 2002/03/09 13:51:20 mohor
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// Status was not latched correctly sometimes. Fixed.
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// Status was not latched correctly sometimes. Fixed.
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| Line 136... |
Line 139... |
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
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MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
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// Register
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// Register
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r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RecSmall,
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r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RecSmall,
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WillSendControlFrame, TxCtrlEndFrm, // igor !!! WillSendControlFrame gre najbrz ven
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WillSendControlFrame, TxCtrlEndFrm, // WillSendControlFrame out ?
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// Interrupts
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// Interrupts
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, TxC_IRQ, RxC_IRQ,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, TxC_IRQ, RxC_IRQ,
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// Rx Status
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// Rx Status
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| Line 765... |
Line 768... |
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assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
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assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
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assign m_wb_sel_o = 4'hf;
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assign m_wb_sel_o = 4'hf;
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reg[3:0] state;
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// Enabling master wishbone access to the memory for two devices TX and RX.
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// Enabling master wishbone access to the memory for two devices TX and RX.
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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| Line 778... |
Line 780... |
MasterWbRX <=#Tp 1'b0;
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MasterWbRX <=#Tp 1'b0;
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m_wb_adr_o <=#Tp 32'h0;
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m_wb_adr_o <=#Tp 32'h0;
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m_wb_cyc_o <=#Tp 1'b0;
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m_wb_cyc_o <=#Tp 1'b0;
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m_wb_stb_o <=#Tp 1'b0;
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m_wb_stb_o <=#Tp 1'b0;
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m_wb_we_o <=#Tp 1'b0;
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m_wb_we_o <=#Tp 1'b0;
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state <=#Tp 4'h0;
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end
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end
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else
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else
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begin
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begin
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// Switching between two stages depends on enable signals
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// Switching between two stages depends on enable signals
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case ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished})
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case ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished})
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| Line 792... |
Line 793... |
MasterWbRX <=#Tp 1'b1;
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MasterWbRX <=#Tp 1'b1;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_cyc_o <=#Tp 1'b1;
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m_wb_cyc_o <=#Tp 1'b1;
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m_wb_stb_o <=#Tp 1'b1;
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m_wb_stb_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b1;
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state <=#Tp 4'h1;
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end
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end
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5'b00_10_0, 5'b00_10_1 :
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5'b00_10_0, 5'b00_10_1 :
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begin
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begin
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MasterWbTX <=#Tp 1'b1; // idle and master read is needed (data read from tx buffer)
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MasterWbTX <=#Tp 1'b1; // idle and master read is needed (data read from tx buffer)
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MasterWbRX <=#Tp 1'b0;
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MasterWbRX <=#Tp 1'b0;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_cyc_o <=#Tp 1'b1;
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m_wb_cyc_o <=#Tp 1'b1;
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m_wb_stb_o <=#Tp 1'b1;
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m_wb_stb_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b0;
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m_wb_we_o <=#Tp 1'b0;
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state <=#Tp 4'h2;
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end
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end
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5'b10_10_1 :
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5'b10_10_1 :
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begin
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begin
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MasterWbTX <=#Tp 1'b1; // master read and master read is needed (data read from tx buffer)
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MasterWbTX <=#Tp 1'b1; // master read and master read is needed (data read from tx buffer)
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MasterWbRX <=#Tp 1'b0;
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MasterWbRX <=#Tp 1'b0;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_cyc_o <=#Tp 1'b1;
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m_wb_cyc_o <=#Tp 1'b1;
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m_wb_stb_o <=#Tp 1'b1;
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m_wb_stb_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b0;
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m_wb_we_o <=#Tp 1'b0;
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state <=#Tp 4'h3;
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end
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end
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5'b01_01_1 :
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5'b01_01_1 :
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begin
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begin
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MasterWbTX <=#Tp 1'b0; // master write and master write is needed (data write to rx buffer)
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MasterWbTX <=#Tp 1'b0; // master write and master write is needed (data write to rx buffer)
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MasterWbRX <=#Tp 1'b1;
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MasterWbRX <=#Tp 1'b1;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_we_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b1;
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state <=#Tp 4'h4;
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end
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end
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5'b10_01_1, 5'b10_11_1 :
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5'b10_01_1, 5'b10_11_1 :
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begin
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begin
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MasterWbTX <=#Tp 1'b0; // master read and master write is needed (data write to rx buffer)
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MasterWbTX <=#Tp 1'b0; // master read and master write is needed (data write to rx buffer)
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MasterWbRX <=#Tp 1'b1;
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MasterWbRX <=#Tp 1'b1;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_adr_o <=#Tp RxPointer;
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m_wb_we_o <=#Tp 1'b1;
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m_wb_we_o <=#Tp 1'b1;
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state <=#Tp 4'h5;
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end
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end
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5'b01_10_1, 5'b01_11_1 :
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5'b01_10_1, 5'b01_11_1 :
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begin
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begin
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MasterWbTX <=#Tp 1'b1; // master write and master read is needed (data read from tx buffer)
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MasterWbTX <=#Tp 1'b1; // master write and master read is needed (data read from tx buffer)
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MasterWbRX <=#Tp 1'b0;
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MasterWbRX <=#Tp 1'b0;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_adr_o <=#Tp TxPointer;
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m_wb_we_o <=#Tp 1'b0;
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m_wb_we_o <=#Tp 1'b0;
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state <=#Tp 4'h6;
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end
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end
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5'b10_00_1, 5'b01_00_1 :
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5'b10_00_1, 5'b01_00_1 :
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begin
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begin
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MasterWbTX <=#Tp 1'b0; // whatever and no master read or write is needed (ack or err comes finishing previous access)
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MasterWbTX <=#Tp 1'b0; // whatever and no master read or write is needed (ack or err comes finishing previous access)
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MasterWbRX <=#Tp 1'b0;
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MasterWbRX <=#Tp 1'b0;
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m_wb_cyc_o <=#Tp 1'b0;
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m_wb_cyc_o <=#Tp 1'b0;
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m_wb_stb_o <=#Tp 1'b0;
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m_wb_stb_o <=#Tp 1'b0;
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state <=#Tp 4'h7;
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end
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end
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default: // Don't touch
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default: // Don't touch
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begin
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begin
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MasterWbTX <=#Tp MasterWbTX;
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MasterWbTX <=#Tp MasterWbTX;
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MasterWbRX <=#Tp MasterWbRX;
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MasterWbRX <=#Tp MasterWbRX;
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m_wb_cyc_o <=#Tp m_wb_cyc_o;
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m_wb_cyc_o <=#Tp m_wb_cyc_o;
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m_wb_stb_o <=#Tp m_wb_stb_o;
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m_wb_stb_o <=#Tp m_wb_stb_o;
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state <=#Tp state;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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| Line 1057... |
Line 1050... |
assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
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assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
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// assign ClearTxBDReady = ~TxUsedData & TxUsedData_q;
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// assign ClearTxBDReady = ~TxUsedData & TxUsedData_q;
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assign TPauseRq = 0; // igor !!! v koncni fazi mora tu biti pause request
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assign TPauseRq = 0;
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assign TxPauseTV[15:0] = TxLength[15:0]; // igor !!! v koncni fazi mora tu biti pause request
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assign TxPauseTV[15:0] = TxLength[15:0];
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// Generating delayed signals
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// Generating delayed signals
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always @ (posedge MTxClk or posedge Reset)
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always @ (posedge MTxClk or posedge Reset)
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begin
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begin
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| Line 1125... |
Line 1118... |
always @ (posedge MTxClk or posedge Reset)
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always @ (posedge MTxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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TxEndFrm <=#Tp 1'b0;
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TxEndFrm <=#Tp 1'b0;
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else
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else
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if(Flop & TxEndFrm | TxAbort | TxRetry_q) // igor !!! zakaj je tu TxRetry_q ?
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if(Flop & TxEndFrm | TxAbort | TxRetry_q)
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TxEndFrm <=#Tp 1'b0;
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TxEndFrm <=#Tp 1'b0;
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else
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else
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if(Flop & LastWord)
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if(Flop & LastWord)
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begin
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begin
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case (TxValidBytesLatched)
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case (TxValidBytesLatched)
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