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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Diff between revs 365 and 367

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Rev 365 Rev 367
Line 253... Line 253...
  // WISHBONE master
  // WISHBONE master
  m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
  m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
  m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
  m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
  m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
  m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
 
 
`ifdef ETH_WISHBONE_B3
 
  m_wb_cti_o, m_wb_bte_o,
  m_wb_cti_o, m_wb_bte_o,
`endif
 
 
 
  //TX
  //TX
  mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
  mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
 
 
  //RX
  //RX
Line 316... Line 314...
input           m_wb_ack_i;
input           m_wb_ack_i;
input           m_wb_err_i;
input           m_wb_err_i;
 
 
wire    [29:0]  m_wb_adr_tmp;
wire    [29:0]  m_wb_adr_tmp;
 
 
`ifdef ETH_WISHBONE_B3
 
output   [2:0]  m_wb_cti_o;   // Cycle Type Identifier
output   [2:0]  m_wb_cti_o;   // Cycle Type Identifier
output   [1:0]  m_wb_bte_o;   // Burst Type Extension
output   [1:0]  m_wb_bte_o;   // Burst Type Extension
`endif
 
 
 
// Tx
// Tx
input           mtx_clk_pad_i; // Transmit clock (from PHY)
input           mtx_clk_pad_i; // Transmit clock (from PHY)
output   [3:0]  mtxd_pad_o;    // Transmit nibble (to PHY)
output   [3:0]  mtxd_pad_o;    // Transmit nibble (to PHY)
output          mtxen_pad_o;   // Transmit enable (to PHY)
output          mtxen_pad_o;   // Transmit enable (to PHY)
Line 1046... Line 1042...
  .m_wb_cyc_o(m_wb_cyc_o),
  .m_wb_cyc_o(m_wb_cyc_o),
  .m_wb_stb_o(m_wb_stb_o),
  .m_wb_stb_o(m_wb_stb_o),
  .m_wb_ack_i(m_wb_ack_i),
  .m_wb_ack_i(m_wb_ack_i),
  .m_wb_err_i(m_wb_err_i),
  .m_wb_err_i(m_wb_err_i),
 
 
`ifdef ETH_WISHBONE_B3
 
  .m_wb_cti_o(m_wb_cti_o),
  .m_wb_cti_o(m_wb_cti_o),
  .m_wb_bte_o(m_wb_bte_o),
  .m_wb_bte_o(m_wb_bte_o),
`endif
 
 
 
    //TX
    //TX
  .MTxClk(mtx_clk_pad_i),
  .MTxClk(mtx_clk_pad_i),
  .TxStartFrm(TxStartFrm),
  .TxStartFrm(TxStartFrm),
  .TxEndFrm(TxEndFrm),
  .TxEndFrm(TxEndFrm),

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