| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.20 2002/08/14 19:31:48 mohor
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// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
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// need to multiply or devide any more.
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//
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// Revision 1.19 2002/07/23 15:28:31 mohor
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// Revision 1.19 2002/07/23 15:28:31 mohor
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// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
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// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
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//
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//
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// Revision 1.18 2002/05/03 10:15:50 mohor
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// Revision 1.18 2002/05/03 10:15:50 mohor
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// Outputs registered. Reset changed for eth_wishbone module.
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// Outputs registered. Reset changed for eth_wishbone module.
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| Line 154... |
Line 158... |
`define ETH_HASH0_ADR 8'h12 // 0x48
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`define ETH_HASH0_ADR 8'h12 // 0x48
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`define ETH_HASH1_ADR 8'h13 // 0x4C
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`define ETH_HASH1_ADR 8'h13 // 0x4C
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`define ETH_MODER_DEF 17'h0A800
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`define ETH_MODER_DEF 17'h0A800
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`define ETH_INT_SOURCE_DEF 32'h00000000
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`define ETH_INT_MASK_DEF 7'h0
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`define ETH_INT_MASK_DEF 7'h0
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`define ETH_IPGT_DEF 7'h12
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`define ETH_IPGT_DEF 7'h12
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`define ETH_IPGR1_DEF 7'h0C
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`define ETH_IPGR1_DEF 7'h0C
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`define ETH_IPGR2_DEF 7'h12
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`define ETH_IPGR2_DEF 7'h12
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`define ETH_PACKETLEN_DEF 32'h00400600
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`define ETH_PACKETLEN_DEF 32'h00400600
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`define ETH_COLLCONF0_DEF 6'h3f
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`define ETH_COLLCONF0_DEF 6'h3f
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`define ETH_COLLCONF1_DEF 4'hF
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`define ETH_COLLCONF1_DEF 4'hF
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`define ETH_TX_BD_NUM_DEF 8'h40
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`define ETH_TX_BD_NUM_DEF 8'h40
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`define ETH_CTRLMODER_DEF 3'h0
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`define ETH_CTRLMODER_DEF 3'h0
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`define ETH_MIIMODER_DEF 11'h064
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`define ETH_MIIMODER_DEF 10'h064
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`define ETH_MIIADDRESS0_DEF 5'h00
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`define ETH_MIIADDRESS0_DEF 5'h00
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`define ETH_MIIADDRESS1_DEF 5'h00
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`define ETH_MIIADDRESS1_DEF 5'h00
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`define ETH_MIITX_DATA_DEF 16'h0000
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`define ETH_MIITX_DATA_DEF 16'h0000
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`define ETH_MIIRX_DATA_DEF 16'h0000
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`define ETH_MIIRX_DATA_DEF 16'h0000
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`define ETH_MIISTATUS_DEF 32'h00000000
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`define ETH_MIISTATUS_DEF 32'h00000000
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| Line 176... |
Line 179... |
`define ETH_MAC_ADDR1_DEF 16'h0000
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`define ETH_MAC_ADDR1_DEF 16'h0000
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`define ETH_HASH0_DEF 32'h00000000
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`define ETH_HASH0_DEF 32'h00000000
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`define ETH_HASH1_DEF 32'h00000000
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`define ETH_HASH1_DEF 32'h00000000
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`define ETH_MODER_WIDTH 17
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`define ETH_INT_SOURCE_WIDTH 7
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`define ETH_INT_MASK_WIDTH 7
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`define ETH_IPGT_WIDTH 7
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`define ETH_IPGR1_WIDTH 7
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`define ETH_IPGR2_WIDTH 7
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`define ETH_PACKETLEN_WIDTH 32
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`define ETH_TX_BD_NUM_WIDTH 8
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`define ETH_CTRLMODER_WIDTH 3
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`define ETH_MIIMODER_WIDTH 10
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`define ETH_MIITX_DATA_WIDTH 16
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`define ETH_MIIRX_DATA_WIDTH 16
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`define ETH_MIISTATUS_WIDTH 3
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`define ETH_MAC_ADDR0_WIDTH 32
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`define ETH_MAC_ADDR1_WIDTH 16
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`define ETH_HASH0_WIDTH 32
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`define ETH_HASH1_WIDTH 32
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// Outputs are registered (uncomment when needed)
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// Outputs are registered (uncomment when needed)
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`define ETH_REGISTERED_OUTPUTS
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`define ETH_REGISTERED_OUTPUTS
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`define TX_FIFO_CNT_WIDTH 5
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`define TX_FIFO_CNT_WIDTH 5
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`define TX_FIFO_DEPTH 16
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`define TX_FIFO_DEPTH 16
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