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URL https://opencores.org/ocsvn/fade_ether_protocol/fade_ether_protocol/trunk

Subversion Repositories fade_ether_protocol

[/] [fade_ether_protocol/] [trunk/] [stable_jumbo_frames_version/] [fpga/] [src/] [AFCK/] [AFCK_fade_top_8ch.vhd] - Diff between revs 42 and 44

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Rev 42 Rev 44
Line 292... Line 292... 
      probe_in6 : in std_logic_vector(7 downto 0);
 
      probe_in6 : in std_logic_vector(7 downto 0);
 
      probe_in7 : in std_logic_vector(7 downto 0)
 
      probe_in7 : in std_logic_vector(7 downto 0)
 
      );
 
      );
 
  end component;
 
  end component;
 
 
 
 
 
 
 
  component i2c_vio_ctrl is
 
 
 
    port (
 
 
 
      clk : in    std_logic;
 
 
 
      scl : inout std_logic;
 
 
 
      sda : inout std_logic);
 
 
 
  end component i2c_vio_ctrl;
 
 
 
 
 
 
 
  component vio_frq is
 
 
 
    port (
 
 
 
      clk       : in std_logic;
 
 
 
      probe_in0 : in std_logic_vector (31 downto 0);
 
 
 
      probe_in1 : in std_logic_vector (31 downto 0));
 
 
 
  end component vio_frq;
 
 
 
 
 
begin  -- beh1
 
begin  -- beh1
 
  si570_oe                  <= '1';
 
  si570_oe                  <= '1';
 
  clk_updaten               <= '1';
 
  clk_updaten               <= '1';
 
  -- Initialization vector
 
  -- Initialization vector
 
  --configuration_vector(0) <= '1';     -- PMA loopback  
  --configuration_vector(0) <= '1';     -- PMA loopback
Line 404... Line 418... 
            tx_disable             => tx_disable(q*N_OF_LINKS+n)
 
            tx_disable             => tx_disable(q*N_OF_LINKS+n)
 
            );
 
            );
 
 
 
 
 
      end generate il1;
 
      end generate il1;
 
      il2 : if n /= 0 generate
 
      il2 : if n /= 0 generate
 
        ten_gig_eth_pcs_pma_1_1 : entity work.ten_gig_eth_pcs_pma_1
 
        ten_gig_eth_pcs_pma_1_1 : ten_gig_eth_pcs_pma_1
 
          port map (
 
          port map (
 
            dclk                 => core_clk156_out(q),
 
            dclk                 => core_clk156_out(q),
 
            rxrecclk_out         => open,  --??
 
            rxrecclk_out         => open,  --??
 
            coreclk              => core_clk156_out(q),
 
            coreclk              => core_clk156_out(q),
 
            txusrclk             => s_txusrclk_out(q),
 
            txusrclk             => s_txusrclk_out(q),
Line 518... Line 532... 
  --core_ready <= core_status(0);
 
  --core_ready <= core_status(0);
 
  clk1     <= boot_clk;
 
  clk1     <= boot_clk;
 
  clk_user <= core_clk156_out;
 
  clk_user <= core_clk156_out;
 
 
 
 
 
  -- Frequency meters
 
  -- Frequency meters
 
  vio_frq_1 : entity work.vio_frq
 
  vio_frq_1 : vio_frq
 
    port map (
 
    port map (
 
      clk       => boot_clk,
 
      clk       => boot_clk,
 
      probe_in0 => clk0_frq,
 
      probe_in0 => clk0_frq,
 
      probe_in1 => clk1_frq);
 
      probe_in1 => clk1_frq);
 
 
 
 
 
  -- Vio Link statuses
 
  -- Vio Link statuses
 
  vio_stat_1 : entity work.vio_stat
 
  vio_stat_1 : vio_stat
 
    port map (
 
    port map (
 
      clk       => boot_clk,
 
      clk       => boot_clk,
 
      probe_in0 => core_status(0),
 
      probe_in0 => core_status(0),
 
      probe_in1 => core_status(1),
 
      probe_in1 => core_status(1),
 
      probe_in2 => core_status(2),
 
      probe_in2 => core_status(2),
Line 538... Line 552... 
      probe_in5 => core_status(5),
 
      probe_in5 => core_status(5),
 
      probe_in6 => core_status(6),
 
      probe_in6 => core_status(6),
 
      probe_in7 => core_status(7));
 
      probe_in7 => core_status(7));
 
 
 
 
 
  -- JTAG<->I2C part for clock-crossbar
 
  -- JTAG<->I2C part for clock-crossbar
 
  i2c_vio_ctrl_1 : entity work.i2c_vio_ctrl
 
  i2c_vio_ctrl_1 : i2c_vio_ctrl
 
    port map (
 
    port map (
 
      clk => boot_clk,
 
      clk => boot_clk,
 
      scl => scl,
 
      scl => scl,
 
      sda => sda);
 
      sda => sda);
 
 
 
 

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