URL https://opencores.org/ocsvn/fade_ether_protocol/fade_ether_protocol/trunk

Subversion Repositories fade_ether_protocol

[/] [fade_ether_protocol/] [trunk/] [stable_jumbo_frames_version/] [fpga/] [src/] [AFCK/] [i2c/] [i2c_vio_ctrl_top.vhd] - Diff between revs 40 and 44

Rev 40	Rev 44
Line 5...	Line 5...
`-- File : i2c_vio_ctrl_top.vhd`	`-- File : i2c_vio_ctrl_top.vhd`
`-- Author : Wojciech M. Zabolotny wzab01<at>gmail.com`	`-- Author : Wojciech M. Zabolotny wzab01<at>gmail.com`
`-- License : PUBLIC DOMAIN`	`-- License : PUBLIC DOMAIN`
`-- Company :`	`-- Company :`
`-- Created : 2015-05-03`	`-- Created : 2015-05-03`
`-- Last update: 2015-05-07`	`-- Last update: 2017-01-22`
`-- Platform :`	`-- Platform :`
`-- Standard : VHDL'93/02`	`-- Standard : VHDL'93/02`
`-------------------------------------------------------------------------------`	`-------------------------------------------------------------------------------`
`-- Description:`	`-- Description:`
`-------------------------------------------------------------------------------`	`-------------------------------------------------------------------------------`
Line 75...	Line 75...
`probe_out5 : out std_logic_vector (0 to 0));`	`probe_out5 : out std_logic_vector (0 to 0));`
`end component vio_0;`	`end component vio_0;`

`begin -- architecture beh`	`begin -- architecture beh`

`vio_0_1 : entity work.vio_0`	`vio_0_1 : vio_0`
`port map (`	`port map (`
`clk => clk,`	`clk => clk,`
`probe_in0 => dout,`	`probe_in0 => dout,`
`probe_out0 => i2c_rst_n,`	`probe_out0 => i2c_rst_n,`
`probe_out1 => din,`	`probe_out1 => din,`