| Line 4... |
Line 4... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File : tb_fifo_srl_uni_1.vhd
|
-- File : tb_fifo_srl_uni_1.vhd
|
-- Author : Tomasz Turek <tomasz.turek@gmail.com>
|
-- Author : Tomasz Turek <tomasz.turek@gmail.com>
|
-- Company : SzuWar INC
|
-- Company : SzuWar INC
|
-- Created : 09:45:13 16-03-2010
|
-- Created : 09:45:13 16-03-2010
|
-- Last update: 23:36:11 20-03-2010
|
-- Last update: 14:49:11 21-03-2010
|
-- Platform : Xilinx ISE 10.1.03
|
-- Platform : Xilinx ISE 10.1.03
|
-- Standard : VHDL'93
|
-- Standard : VHDL'93
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Description:
|
-- Description:
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
| Line 36... |
Line 36... |
component fifo_srl_uni is
|
component fifo_srl_uni is
|
|
|
generic (
|
generic (
|
iDataWidth : integer range 1 to 32 := 17;
|
iDataWidth : integer range 1 to 32 := 17;
|
ififoWidth : integer range 1 to 1023 := 33;
|
ififoWidth : integer range 1 to 1023 := 33;
|
iInputReg : integer range 0 to 2 := 0;
|
iInputReg : integer range 0 to 3 := 0;
|
iOutputReg : integer range 0 to 3 := 2;
|
iOutputReg : integer range 0 to 3 := 2;
|
iFullFlagOfSet : integer range 0 to 1021 := 2;
|
iFullFlagOfSet : integer range 0 to 1021 := 2;
|
iEmptyFlagOfSet : integer range 0 to 1021 := 5;
|
iEmptyFlagOfSet : integer range 0 to 1021 := 5;
|
iSizeDelayCounter : integer range 5 to 11 := 6
|
iSizeDelayCounter : integer range 5 to 11 := 6
|
);
|
);
|
| Line 61... |
Line 61... |
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- constants --
|
-- constants --
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
constant iDataWidth : integer := 16;
|
constant iDataWidth : integer := 16;
|
constant ififoWidth : integer := 8;
|
constant ififoWidth : integer := 33;
|
constant iInputReg : integer := 0;
|
constant iInputReg : integer := 3;
|
constant iOutputReg : integer := 1;
|
constant iOutputReg : integer := 3;
|
constant iFullFlagOfSet : integer := 0;
|
constant iFullFlagOfSet : integer := 0;
|
constant iEmptyFlagOfSet : integer := 0;
|
constant iEmptyFlagOfSet : integer := 0;
|
constant iSizeDelayCounter : integer := 5;
|
constant iSizeDelayCounter : integer := 6;
|
|
|
constant iWriteDataCounter : integer := 10;
|
constant iWriteDataCounter : integer := 22;
|
constant iReadDataCounter : integer := 13;
|
constant iReadDataCounter : integer := 33;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- signals --
|
-- signals --
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- IN --
|
-- IN --
|
| Line 153... |
Line 153... |
READ_ENABLE_I <= '0';
|
READ_ENABLE_I <= '0';
|
i_count_write <= i_count_write + 1;
|
i_count_write <= i_count_write + 1;
|
|
|
else
|
else
|
|
|
|
DATA_I <= DATA_I;
|
|
WRITE_ENABLE_I <= '0';
|
|
READ_ENABLE_I <= '0';
|
v_count <= v_count + 1;
|
v_count <= v_count + 1;
|
|
|
end if;
|
end if;
|
|
|
when x"0002" =>
|
when x"0002" =>
|
| Line 182... |
Line 185... |
|
|
when x"0005" =>
|
when x"0005" =>
|
|
|
DATA_I <= x"0100";
|
DATA_I <= x"0100";
|
WRITE_ENABLE_I <= '1';
|
WRITE_ENABLE_I <= '1';
|
READ_ENABLE_I <= '0';
|
READ_ENABLE_I <= '1';
|
v_count <= v_count + 1;
|
v_count <= v_count + 1;
|
|
|
when x"0006" =>
|
when x"0006" =>
|
|
|
DATA_I <= x"0000";
|
DATA_I <= x"0000";
|
