Line 4... |
Line 4... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File : tb_fifo_srl_uni_1.vhd
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-- File : tb_fifo_srl_uni_1.vhd
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-- Author : Tomasz Turek <tomasz.turek@gmail.com>
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-- Author : Tomasz Turek <tomasz.turek@gmail.com>
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-- Company : SzuWar INC
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-- Company : SzuWar INC
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-- Created : 09:45:13 16-03-2010
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-- Created : 09:45:13 16-03-2010
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-- Last update: 23:36:11 20-03-2010
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-- Last update: 14:49:11 21-03-2010
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-- Platform : Xilinx ISE 10.1.03
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-- Platform : Xilinx ISE 10.1.03
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-- Standard : VHDL'93
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-- Standard : VHDL'93
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-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Description:
|
-- Description:
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
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Line 36... |
Line 36... |
component fifo_srl_uni is
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component fifo_srl_uni is
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|
|
generic (
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generic (
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iDataWidth : integer range 1 to 32 := 17;
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iDataWidth : integer range 1 to 32 := 17;
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ififoWidth : integer range 1 to 1023 := 33;
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ififoWidth : integer range 1 to 1023 := 33;
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iInputReg : integer range 0 to 2 := 0;
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iInputReg : integer range 0 to 3 := 0;
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iOutputReg : integer range 0 to 3 := 2;
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iOutputReg : integer range 0 to 3 := 2;
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iFullFlagOfSet : integer range 0 to 1021 := 2;
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iFullFlagOfSet : integer range 0 to 1021 := 2;
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iEmptyFlagOfSet : integer range 0 to 1021 := 5;
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iEmptyFlagOfSet : integer range 0 to 1021 := 5;
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iSizeDelayCounter : integer range 5 to 11 := 6
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iSizeDelayCounter : integer range 5 to 11 := 6
|
);
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);
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Line 61... |
Line 61... |
|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
-- constants --
|
-- constants --
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
constant iDataWidth : integer := 16;
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constant iDataWidth : integer := 16;
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constant ififoWidth : integer := 8;
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constant ififoWidth : integer := 33;
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constant iInputReg : integer := 0;
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constant iInputReg : integer := 3;
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constant iOutputReg : integer := 1;
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constant iOutputReg : integer := 3;
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constant iFullFlagOfSet : integer := 0;
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constant iFullFlagOfSet : integer := 0;
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constant iEmptyFlagOfSet : integer := 0;
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constant iEmptyFlagOfSet : integer := 0;
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constant iSizeDelayCounter : integer := 5;
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constant iSizeDelayCounter : integer := 6;
|
|
|
constant iWriteDataCounter : integer := 10;
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constant iWriteDataCounter : integer := 22;
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constant iReadDataCounter : integer := 13;
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constant iReadDataCounter : integer := 33;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- signals --
|
-- signals --
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- IN --
|
-- IN --
|
Line 153... |
Line 153... |
READ_ENABLE_I <= '0';
|
READ_ENABLE_I <= '0';
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i_count_write <= i_count_write + 1;
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i_count_write <= i_count_write + 1;
|
|
|
else
|
else
|
|
|
|
DATA_I <= DATA_I;
|
|
WRITE_ENABLE_I <= '0';
|
|
READ_ENABLE_I <= '0';
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v_count <= v_count + 1;
|
v_count <= v_count + 1;
|
|
|
end if;
|
end if;
|
|
|
when x"0002" =>
|
when x"0002" =>
|
Line 182... |
Line 185... |
|
|
when x"0005" =>
|
when x"0005" =>
|
|
|
DATA_I <= x"0100";
|
DATA_I <= x"0100";
|
WRITE_ENABLE_I <= '1';
|
WRITE_ENABLE_I <= '1';
|
READ_ENABLE_I <= '0';
|
READ_ENABLE_I <= '1';
|
v_count <= v_count + 1;
|
v_count <= v_count + 1;
|
|
|
when x"0006" =>
|
when x"0006" =>
|
|
|
DATA_I <= x"0000";
|
DATA_I <= x"0000";
|