| Line 2... |
Line 2... |
--| @file h2.vhd
|
--| @file h2.vhd
|
--| @brief The H2 Processor: J1 processor translation and extension.
|
--| @brief The H2 Processor: J1 processor translation and extension.
|
--| Moved bit 12 to bit 4 to allow for more ALU instructions.
|
--| Moved bit 12 to bit 4 to allow for more ALU instructions.
|
--|
|
--|
|
--| @author Richard James Howe.
|
--| @author Richard James Howe.
|
--| @copyright Copyright 2017 Richard James Howe.
|
--| @copyright Copyright 2017, 2019 Richard James Howe.
|
--| @license MIT
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--| @license MIT
|
--| @email howe.r.j.89@gmail.com
|
--| @email howe.r.j.89@gmail.com
|
--|
|
--|
|
|
--| NB. It would be nice to be able to specify the CPU word length with a
|
|
--| generic, so we could instantiate a 32-bit CPU if we wanted to.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
library ieee,work,std;
|
library ieee,work,std;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
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|
|
package h2_pkg is
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package h2_pkg is
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subtype word is std_ulogic_vector(15 downto 0);
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subtype word is std_ulogic_vector(15 downto 0);
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subtype address is std_ulogic_vector(12 downto 0);
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subtype address is std_ulogic_vector(12 downto 0);
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|
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constant hardware_cpu_id: word := X"CAFE";
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constant hardware_cpu_id: word := X"0666";
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constant simulation_cpu_id: word := X"DEAD";
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constant simulation_cpu_id: word := X"1984";
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|
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component h2 is
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component h2 is
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generic(
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generic(
|
|
asynchronous_reset: boolean := true; -- use asynchronous reset if true, synchronous if false
|
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delay: time := 0 ns; -- simulation only, gate delay
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|
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cpu_id: word := hardware_cpu_id; -- Value for the CPU ID instruction
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cpu_id: word := hardware_cpu_id; -- Value for the CPU ID instruction
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interrupt_address_length: positive := 3; -- Log_2 of the number of interrupts
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interrupt_address_length: positive := 3; -- Log_2 of the number of interrupts
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start_address: natural := 0; -- Initial program counter value
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start_address: natural := 0; -- Initial program counter value
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stack_size_log2: positive := 6; -- Log_2 of the Size of the stack
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stack_size_log2: positive := 6; -- Log_2 of the Size of the stack
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use_interrupts: boolean := true); -- Enable Interrupts in the H2 Core
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use_interrupts: boolean := true -- Enable Interrupts in the H2 Core
|
|
);
|
port(
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port(
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clk: in std_ulogic;
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clk: in std_ulogic;
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rst: in std_ulogic;
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rst: in std_ulogic; -- active high reset, configurable async/sync
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|
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-- IO interface
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stop: in std_ulogic; -- Assert high to halt the H2 core
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stop: in std_ulogic; -- Assert high to halt the H2 core
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|
|
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-- IO interface
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io_wr: out std_ulogic; -- Output Write Enable
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io_wr: out std_ulogic; -- Output Write Enable
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io_re: out std_ulogic; -- Input Read Enable
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io_re: out std_ulogic; -- Input Read Enable
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io_din: in word; -- Data Input from register
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io_din: in word; -- Data Input from register
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io_dout: out word; -- Data Output to register
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io_dout: out word; -- Data Output to register
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io_daddr: out word; -- Data Address for I/O action
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io_daddr: out word; -- Data Address for I/O action
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| Line 62... |
Line 67... |
use ieee.math_real.all; -- only needed for calculations relating to generics
|
use ieee.math_real.all; -- only needed for calculations relating to generics
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use work.h2_pkg.all;
|
use work.h2_pkg.all;
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|
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entity h2 is
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entity h2 is
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generic(
|
generic(
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|
asynchronous_reset: boolean := true; -- use asynchronous reset if true, synchronous if false
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delay: time := 0 ns; -- simulation only, gate delay
|
|
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cpu_id: word := hardware_cpu_id; -- Value for the CPU ID instruction
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cpu_id: word := hardware_cpu_id; -- Value for the CPU ID instruction
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interrupt_address_length: positive := 3; -- Log_2 of the number of interrupts
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interrupt_address_length: positive := 3; -- Log_2 of the number of interrupts
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start_address: natural := 0; -- Initial program counter value
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start_address: natural := 0; -- Initial program counter value
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stack_size_log2: positive := 6; -- Log_2 of the Size of the stack
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stack_size_log2: positive := 6; -- Log_2 of the Size of the stack
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use_interrupts: boolean := true); -- Enable Interrupts in the H2 Core
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use_interrupts: boolean := true); -- Enable Interrupts in the H2 Core
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| Line 95... |
Line 103... |
dout: out word; -- RAM data output
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dout: out word; -- RAM data output
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daddr: out address); -- RAM address
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daddr: out address); -- RAM address
|
end;
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end;
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|
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architecture rtl of h2 is
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architecture rtl of h2 is
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|
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signal pc_c: address := std_ulogic_vector(to_unsigned(start_address, address'length));
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signal pc_c: address := std_ulogic_vector(to_unsigned(start_address, address'length));
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signal pc_n: address := (others => '0');
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signal pc_n: address := (others => '0');
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signal pc_plus_one: address := (others => '0');
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signal pc_plus_one: address := (others => '0');
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|
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constant stack_size: integer := 2 ** stack_size_log2;
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constant stack_size: integer := 2 ** stack_size_log2;
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| Line 123... |
Line 130... |
branch0: std_ulogic;
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branch0: std_ulogic;
|
call: std_ulogic;
|
call: std_ulogic;
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end record;
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end record;
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|
|
signal is_instr: instruction_info_type := ('0', '0', '0', '0', '0');
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signal is_instr: instruction_info_type := ('0', '0', '0', '0', '0');
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|
|
signal is_interrupt: std_ulogic := '0';
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signal is_interrupt: std_ulogic := '0';
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signal is_ram_write: std_ulogic := '0';
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signal is_ram_write: std_ulogic := '0';
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|
|
type compare_type is record
|
type compare_type is record
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more: std_ulogic;
|
more: std_ulogic; -- signed greater than; T > N?
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equal: std_ulogic;
|
equal: std_ulogic; -- equality; N = T?
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umore: std_ulogic;
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umore: std_ulogic; -- unsigned greater than; T > N?
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zero: std_ulogic;
|
zero: std_ulogic; -- zero test; T = 0?
|
end record;
|
end record;
|
|
|
signal compare: compare_type := ('0', '0', '0', '0');
|
signal compare: compare_type := ('0', '0', '0', '0');
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|
|
signal int_en_c, int_en_n: std_ulogic := '0'; -- interrupt enable
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signal stop_c: std_ulogic := '1'; -- processor wait state register (current)
|
signal irq_c, irq_n: std_ulogic := '0'; -- interrupt request
|
signal stop_n: std_ulogic := '0'; -- processor wait state register (next)
|
signal irq_addr_c, irq_addr_n: std_ulogic_vector(irq_addr'range) := (others => '0');
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|
|
signal irq_en_c, irq_en_n: std_ulogic := '0'; -- interrupt enable
|
|
signal irq_c, irq_n: std_ulogic := '0'; -- pending interrupt request
|
|
signal irq_addr_c, irq_addr_n: std_ulogic_vector(irq_addr'range) := (others => '0'); -- address of pending interrupt request vector
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|
|
signal tos_c, tos_n: word := (others => '0'); -- top of stack
|
signal tos_c, tos_n: word := (others => '0'); -- top of stack
|
signal nos: word := (others => '0'); -- next on stack
|
signal nos: word := (others => '0'); -- next on stack
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signal rtos_c: word := (others => '0'); -- top of return stack
|
signal rtos_c: word := (others => '0'); -- top of return stack
|
signal rstk_data: word := (others => '0'); -- return stack input
|
signal rstk_data: word := (others => '0'); -- return stack input
|
signal aluop: std_ulogic_vector(4 downto 0) := (others => '0'); -- ALU operation
|
signal aluop: std_ulogic_vector(4 downto 0) := (others => '0'); -- ALU operation
|
|
|
|
signal instruction: word := (others => '0'); -- processed 'insn'
|
begin
|
begin
|
assert stack_size > 4 report "stack size too small: " & integer'image(stack_size) severity failure;
|
assert stack_size > 4 report "stack size too small: " & integer'image(stack_size) severity failure;
|
|
-- assert dd /= "10" severity warning; -- valid, but odd (now used)
|
|
|
is_instr.alu <= '1' when insn(15 downto 13) = "011" else '0';
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is_instr.branch <= '1' when instruction(15 downto 13) = "000" else '0' after delay;
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is_instr.lit <= '1' when insn(15) = '1' else '0';
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is_instr.branch0 <= '1' when instruction(15 downto 13) = "001" else '0' after delay;
|
is_instr.branch <= '1' when insn(15 downto 13) = "000" else '0';
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is_instr.call <= '1' when instruction(15 downto 13) = "010" else '0' after delay;
|
is_instr.branch0 <= '1' when insn(15 downto 13) = "001" else '0';
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is_instr.alu <= '1' when instruction(15 downto 13) = "011" else '0' after delay;
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is_instr.call <= '1' when insn(15 downto 13) = "010" else '0';
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is_instr.lit <= '1' when instruction(15) = '1' else '0' after delay;
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is_interrupt <= '1' when irq_c = '1' and int_en_c = '1' and use_interrupts else '0';
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is_ram_write <= '1' when is_instr.alu = '1' and instruction(5) = '1' else '0' after delay;
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is_ram_write <= '1' when is_interrupt = '0' and is_instr.alu = '1' and insn(5) = '1' else '0';
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compare.more <= '1' when signed(tos_c) > signed(nos) else '0' after delay;
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compare.more <= '1' when signed(tos_c) > signed(nos) else '0';
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compare.umore <= '1' when unsigned(tos_c) > unsigned(nos) else '0' after delay;
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compare.umore <= '1' when unsigned(tos_c) > unsigned(nos) else '0';
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compare.equal <= '1' when tos_c = nos else '0' after delay;
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compare.equal <= '1' when tos_c = nos else '0';
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compare.zero <= '1' when unsigned(tos_c(15 downto 0)) = 0 else '0' after delay;
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compare.zero <= '1' when unsigned(tos_c(15 downto 0)) = 0 else '0';
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nos <= vstk_ram(to_integer(vstkp_c)) after delay;
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nos <= vstk_ram(to_integer(vstkp_c));
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rtos_c <= rstk_ram(to_integer(rstkp_c)) after delay;
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rtos_c <= rstk_ram(to_integer(rstkp_c));
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pc <= pc_n after delay;
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pc <= pc_n;
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pc_plus_one <= std_ulogic_vector(unsigned(pc_c) + 1) after delay;
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pc_plus_one <= std_ulogic_vector(unsigned(pc_c) + 1);
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dout <= nos after delay;
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dout <= nos;
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daddr <= tos_c(13 downto 1) when is_ram_write = '1' else tos_n(13 downto 1) after delay;
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daddr <= tos_c(13 downto 1) when is_ram_write = '1' else tos_n(13 downto 1);
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dwe <= '1' when is_ram_write = '1' and tos_c(15 downto 14) = "00" else '0' after delay;
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dwe <= '1' when is_ram_write = '1' and tos_c(15 downto 14) = "00" else '0';
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dre <= '1' when tos_n(15 downto 14) = "00" else '0' after delay;
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dre <= '1' when tos_n(15 downto 14) = "00" else '0';
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io_dout <= nos after delay;
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io_dout <= nos;
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io_daddr <= tos_c after delay;
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io_daddr <= tos_c;
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io_wr <= '1' when is_ram_write = '1' and tos_c(15 downto 14) /= "00" else '0' after delay;
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io_wr <= '1' when is_ram_write = '1' and tos_c(15 downto 14) /= "00" else '0';
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is_interrupt <= '1' when irq_c = '1' and irq_en_c = '1' and use_interrupts else '0' after delay;
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dd <= (0 => insn(0), others => insn(1)); -- sign extend
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irq_n <= irq after delay;
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rd <= (0 => insn(2), others => insn(3)); -- sign extend
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irq_addr_n <= irq_addr after delay;
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dstk_we <= '1' when is_interrupt = '0' and (is_instr.lit = '1' or (is_instr.alu = '1' and insn(7) = '1')) else '0';
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stop_n <= stop after delay;
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dd(0) <= instruction(0) after delay;
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rd(0) <= instruction(2) after delay;
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dd(dd'high downto 1) <= (others => '1') when instruction(1) = '1' else (others => '0') after delay; -- sign extend
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rd(rd'high downto 1) <= (others => '1') when instruction(3) = '1' else (others => '0') after delay; -- sign extend
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dstk_we <= '1' when (is_instr.lit = '1' or (is_instr.alu = '1' and instruction(7) = '1')) else '0' after delay;
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|
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next_state: process(clk, rst)
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next_state: process(clk, rst)
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procedure reset is
|
begin
|
begin
|
if rst = '1' then
|
pc_c <= std_ulogic_vector(to_unsigned(start_address, pc_c'length)) after delay;
|
vstkp_c <= (others => '0');
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stop_c <= '1' after delay; -- start in stopped state
|
rstkp_c <= (others => '0');
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vstkp_c <= (others => '0') after delay;
|
pc_c <= std_ulogic_vector(to_unsigned(start_address, pc_c'length));
|
rstkp_c <= (others => '0') after delay;
|
tos_c <= (others => '0');
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tos_c <= (others => '0') after delay;
|
int_en_c <= '0';
|
irq_addr_c <= (others => '0') after delay;
|
irq_c <= '0';
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irq_en_c <= '0' after delay;
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irq_addr_c <= (others => '0');
|
irq_c <= '0' after delay;
|
|
end reset;
|
|
begin
|
|
if rst = '1' and asynchronous_reset then
|
|
reset;
|
elsif rising_edge(clk) then
|
elsif rising_edge(clk) then
|
vstkp_c <= vstkp_n;
|
if rst = '1' and not asynchronous_reset then
|
rstkp_c <= rstkp_n;
|
reset;
|
pc_c <= pc_n;
|
else
|
tos_c <= tos_n;
|
assert stop_c = '0' or (stop_c = '1' and is_instr.branch = '1') severity failure;
|
int_en_c <= int_en_n;
|
assert (not rstk_we = '1') or (((is_instr.alu = '1' and instruction(6) = '1') or is_instr.call = '1')) severity failure;
|
irq_c <= irq_n;
|
assert (not dstk_we = '1') or (((is_instr.alu = '1' and instruction(7) = '1') or is_instr.lit = '1')) severity failure;
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irq_addr_c <= irq_addr_n;
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|
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pc_c <= pc_n after delay;
|
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stop_c <= stop_n after delay;
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vstkp_c <= vstkp_n after delay;
|
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rstkp_c <= rstkp_n after delay;
|
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tos_c <= tos_n after delay;
|
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irq_addr_c <= irq_addr_n after delay;
|
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irq_en_c <= irq_en_n after delay;
|
|
irq_c <= irq_n after delay;
|
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
stack_write: process(clk)
|
stack_write: process(clk)
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
if dstk_we = '1' then
|
if dstk_we = '1' then
|
vstk_ram(to_integer(vstkp_n)) <= tos_c;
|
vstk_ram(to_integer(vstkp_n)) <= tos_c after delay;
|
end if;
|
end if;
|
if rstk_we = '1' then
|
if rstk_we = '1' then
|
rstk_ram(to_integer(rstkp_n)) <= rstk_data;
|
rstk_ram(to_integer(rstkp_n)) <= rstk_data after delay;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
alu_select: process(insn, is_instr, is_interrupt)
|
decode: process(insn, irq_addr_c, is_interrupt, stop_c, pc_c)
|
begin
|
begin
|
if is_interrupt = '1' or is_instr.call = '1' or is_instr.branch = '1' then
|
if stop_c = '1' then -- assert a BRANCH instruction to current location on CPU halt
|
aluop <= (others => '0');
|
instruction <= "000" & pc_c after delay;
|
|
elsif is_interrupt = '1' then -- assemble a CALL instruction on interrupt
|
|
instruction <= (others => '0') after delay;
|
|
instruction(15 downto 13) <= "010" after delay; -- turn into a CALL
|
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instruction(irq_addr_c'range) <= irq_addr_c after delay; -- address to call
|
|
else
|
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instruction <= insn after delay;
|
|
end if;
|
|
end process;
|
|
|
|
alu_select: process(instruction, is_instr)
|
|
begin
|
|
if is_instr.lit = '1' then
|
|
aluop <= "10101" after delay;
|
elsif is_instr.branch0 = '1' then
|
elsif is_instr.branch0 = '1' then
|
aluop <= (0 => '1', others => '0');
|
aluop <= (0 => '1', others => '0') after delay;
|
elsif is_instr.alu = '1' then
|
elsif is_instr.alu = '1' then
|
aluop <= insn(12 downto 8);
|
aluop <= instruction(12 downto 8) after delay;
|
else
|
else
|
aluop <= (others => '0');
|
aluop <= (others => '0') after delay;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
alu: process(
|
alu_unit: process(
|
is_instr.lit,
|
|
tos_c, nos, rtos_c,
|
tos_c, nos, rtos_c,
|
din, insn, aluop,
|
din, instruction, aluop,
|
io_din,
|
io_din,
|
vstkp_c, rstkp_c,
|
vstkp_c, rstkp_c,
|
compare,
|
compare,
|
int_en_c,
|
irq_en_c)
|
stop)
|
|
begin
|
begin
|
io_re <= '0'; -- hardware reads can have side effects
|
io_re <= '0'; -- hardware reads can have side effects
|
tos_n <= tos_c;
|
tos_n <= tos_c;
|
int_en_n <= int_en_c;
|
irq_en_n <= irq_en_c;
|
if stop = '1' then
|
|
null;
|
|
elsif is_instr.lit = '1' then
|
|
tos_n <= "0" & insn(14 downto 0);
|
|
else
|
|
case aluop is
|
case aluop is
|
when "00000" => tos_n <= tos_c;
|
-- Register Operations
|
when "00001" => tos_n <= nos;
|
when "00000" => tos_n <= tos_c after delay;
|
when "01011" => tos_n <= rtos_c;
|
when "00001" => tos_n <= nos after delay;
|
when "10100" => tos_n <= cpu_id;
|
when "01011" => tos_n <= rtos_c after delay;
|
|
when "10100" => tos_n <= cpu_id after delay;
|
when "00011" => tos_n <= tos_c and nos;
|
when "10101" => tos_n <= "0" & instruction(14 downto 0) after delay; -- undocumented, may be removed
|
when "00100" => tos_n <= tos_c or nos;
|
-- Logical Operations
|
when "00101" => tos_n <= tos_c xor nos;
|
when "00011" => tos_n <= tos_c and nos after delay;
|
when "00110" => tos_n <= not tos_c;
|
when "00100" => tos_n <= tos_c or nos after delay;
|
|
when "00101" => tos_n <= tos_c xor nos after delay;
|
when "00111" => tos_n <= (others => compare.equal);
|
when "00110" => tos_n <= not tos_c after delay;
|
when "01000" => tos_n <= (others => compare.more);
|
-- Comparison Operations
|
when "01111" => tos_n <= (others => compare.umore);
|
when "00111" => tos_n <= (others => compare.equal) after delay;
|
when "10011" => tos_n <= (others => compare.zero);
|
when "01000" => tos_n <= (others => compare.more) after delay;
|
|
when "01111" => tos_n <= (others => compare.umore) after delay;
|
when "01001" => tos_n <= word(unsigned(nos) srl to_integer(unsigned(tos_c(3 downto 0))));
|
when "10011" => tos_n <= (others => compare.zero) after delay;
|
when "01101" => tos_n <= word(unsigned(nos) sll to_integer(unsigned(tos_c(3 downto 0))));
|
-- Arithmetic Operations
|
when "00010" => tos_n <= word(unsigned(nos) + unsigned(tos_c));
|
when "01001" => tos_n <= word(unsigned(nos) srl to_integer(unsigned(tos_c(3 downto 0)))) after delay;
|
when "01010" => tos_n <= word(unsigned(tos_c) - 1);
|
when "01101" => tos_n <= word(unsigned(nos) sll to_integer(unsigned(tos_c(3 downto 0)))) after delay;
|
|
when "00010" => tos_n <= word(unsigned(nos) + unsigned(tos_c)) after delay;
|
when "01100" =>
|
when "01010" => tos_n <= word(unsigned(tos_c) - 1) after delay;
|
-- input: 0x4000 - 0x7FFF is external input
|
-- Input (output is handled elsewhere)
|
|
when "01100" => -- input: 0x4000 - 0x7FFF is external input
|
if tos_c(15 downto 14) /= "00" then
|
if tos_c(15 downto 14) /= "00" then
|
tos_n <= io_din;
|
tos_n <= io_din after delay;
|
io_re <= '1';
|
io_re <= '1' after delay;
|
else
|
else
|
tos_n <= din;
|
tos_n <= din after delay;
|
end if;
|
end if;
|
when "01110" => tos_n <= (others => '0');
|
-- Stack Depth
|
tos_n(vstkp_c'range) <= std_ulogic_vector(vstkp_c);
|
when "01110" => tos_n <= (others => '0') after delay;
|
when "10010" => tos_n <= (others => '0');
|
tos_n(vstkp_c'range) <= std_ulogic_vector(vstkp_c) after delay;
|
tos_n(rstkp_c'range) <= std_ulogic_vector(rstkp_c);
|
when "10010" => tos_n <= (others => '0') after delay;
|
|
tos_n(rstkp_c'range) <= std_ulogic_vector(rstkp_c) after delay;
|
when "10001" => tos_n <= (others => int_en_c);
|
-- CPU Status Set/Get
|
when "10000" => int_en_n <= tos_c(0);
|
when "10001" => tos_n <= (others => '0') after delay;
|
|
tos_n(0) <= irq_en_c after delay;
|
when others => tos_n <= tos_c;
|
when "10000" => tos_n <= nos after delay;
|
|
irq_en_n <= tos_c(0) after delay;
|
|
-- Default/Invalid instructions
|
|
when others => tos_n <= tos_c after delay;
|
report "Invalid ALU operation: " & integer'image(to_integer(unsigned(aluop))) severity error;
|
report "Invalid ALU operation: " & integer'image(to_integer(unsigned(aluop))) severity error;
|
end case;
|
end case;
|
end if;
|
|
end process;
|
end process;
|
|
|
stack_update: process(
|
stack_update: process(
|
pc_c, insn, tos_c,
|
pc_c, instruction, tos_c,
|
vstkp_c, dd,
|
vstkp_c, dd,
|
rstkp_c, rd,
|
rstkp_c, rd,
|
is_instr, is_interrupt, pc_plus_one, stop)
|
is_instr, pc_plus_one, is_interrupt)
|
begin
|
begin
|
vstkp_n <= vstkp_c;
|
vstkp_n <= vstkp_c;
|
rstkp_n <= rstkp_c;
|
rstkp_n <= rstkp_c;
|
rstk_we <= '0';
|
rstk_we <= '0';
|
rstk_data <= "00" & pc_plus_one & "0";
|
rstk_data <= "00" & pc_plus_one & "0";
|
|
|
if stop = '1' then -- Do nothing
|
if is_instr.lit = '1' then
|
null;
|
|
elsif is_interrupt = '1' then -- Interrupts are similar to a call
|
|
rstkp_n <= rstkp_c + 1;
|
|
rstk_we <= '1';
|
|
rstk_data <= "00" & pc_c & "0";
|
|
elsif is_instr.lit = '1' then
|
|
assert to_integer(vstkp_c) + 1 < stack_size;
|
assert to_integer(vstkp_c) + 1 < stack_size;
|
vstkp_n <= vstkp_c + 1;
|
vstkp_n <= vstkp_c + 1 after delay;
|
elsif is_instr.alu = '1' then
|
end if;
|
assert (not insn(6) = '1') or ((to_integer(rstkp_c) + to_integer(signed(rd))) < stack_size);
|
if is_instr.alu = '1' then
|
|
assert (not instruction(6) = '1') or ((to_integer(rstkp_c) + to_integer(signed(rd))) < stack_size);
|
assert ((to_integer(vstkp_c) + to_integer(signed(dd))) < stack_size);
|
assert ((to_integer(vstkp_c) + to_integer(signed(dd))) < stack_size);
|
rstk_we <= insn(6);
|
rstk_we <= instruction(6) after delay;
|
rstk_data <= tos_c;
|
rstk_data <= tos_c after delay;
|
vstkp_n <= vstkp_c + unsigned(dd);
|
vstkp_n <= vstkp_c + unsigned(dd) after delay;
|
rstkp_n <= rstkp_c + unsigned(rd);
|
rstkp_n <= rstkp_c + unsigned(rd) after delay;
|
elsif is_instr.branch0 = '1' then
|
end if;
|
vstkp_n <= vstkp_c - 1;
|
if is_instr.branch0 = '1' then
|
elsif is_instr.call = '1' then
|
vstkp_n <= (vstkp_c - 1) after delay;
|
rstkp_n <= rstkp_c + 1;
|
end if;
|
rstk_we <= '1';
|
if is_instr.call = '1' then
|
|
if is_interrupt = '1' then
|
|
rstk_data <= "00" & pc_c & "0" after delay;
|
|
end if;
|
|
rstkp_n <= rstkp_c + 1 after delay;
|
|
rstk_we <= '1' after delay;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
pc_update: process(
|
pc_update: process(
|
pc_c,insn, rtos_c, pc_plus_one,
|
instruction, rtos_c, pc_plus_one,
|
is_instr,
|
is_instr,
|
is_interrupt, irq_c, irq_addr_c, irq_addr,irq,
|
compare.zero)
|
compare.zero,
|
|
stop)
|
|
begin
|
begin
|
pc_n <= pc_c;
|
|
irq_n <= irq_c;
|
|
irq_addr_n <= irq_addr_c;
|
|
irq_n <= irq;
|
|
|
|
if irq = '1' then irq_addr_n <= irq_addr; end if;
|
|
|
|
if stop = '1' then
|
|
null;
|
|
elsif is_interrupt = '1' then -- Update PC on interrupt
|
|
irq_n <= '0';
|
|
irq_addr_n <= (others => '0');
|
|
pc_n <= (others => '0');
|
|
pc_n(irq_addr'range) <= irq_addr_c;
|
|
else -- Update PC on normal operations
|
|
pc_n <= pc_plus_one;
|
|
if is_instr.branch = '1' or (is_instr.branch0 = '1' and compare.zero = '1') or is_instr.call = '1' then
|
if is_instr.branch = '1' or (is_instr.branch0 = '1' and compare.zero = '1') or is_instr.call = '1' then
|
pc_n <= insn(12 downto 0);
|
pc_n <= instruction(12 downto 0) after delay;
|
elsif is_instr.alu = '1' and insn(4) = '1' then
|
elsif is_instr.alu = '1' and instruction(4) = '1' then
|
pc_n <= rtos_c(13 downto 1);
|
pc_n <= rtos_c(13 downto 1) after delay;
|
end if;
|
else
|
|
pc_n <= pc_plus_one after delay;
|
end if;
|
end if;
|
end process;
|
end process;
|
end architecture;
|
end architecture;
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
