| Line 12... |
Line 12... |
--| The devices are:
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--| The devices are:
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--| - PC28F128P33BF60 (Non-Volatile Flash with a CSI Interface)
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--| - PC28F128P33BF60 (Non-Volatile Flash with a CSI Interface)
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--| - MT45W1MW16BDGB (SRAM)
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--| - MT45W1MW16BDGB (SRAM)
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--|
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--|
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--| They both share the same data, address lines, output enable, and write
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--| They both share the same data, address lines, output enable, and write
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--| enable signals. They are selected with a Chip Select (RamCS = SRAM,
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--| enable signals. They are selected with a Chip Select (ram_cs = SRAM,
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--| FlashCS = Flash device). The Flash has an addition reset line (FlashRP).
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--| flash_cs = Flash device). The Flash has an addition reset line (flash_rp).
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--|
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--|
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--| This interface is very simple, it does not bother with timing and
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--| This interface is very simple, it does not bother with timing and
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--| only has minimal logic and state, it is up to the consumer of this
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--| only has minimal logic and state, it is up to the consumer of this
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--| module to implement the bus timing - which in this case is a Soft CPU
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--| module to implement the bus timing - which in this case is a Soft CPU
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--| Core.
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--| Core.
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--|
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--|
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--| Many improvements could be made, we could do a lot more in the hardware,
|
|
--| even going as far as to implement most of the Common Flash Interface (but
|
|
--| that would be better placed in a controlling module), but it is not
|
|
--| necessary. We will Keep It Simple.
|
|
--|
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee,work;
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library ieee,work;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.util.common_generics;
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|
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entity ram_interface is
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entity ram_interface is
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|
generic (g: common_generics);
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port(
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port(
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clk: in std_ulogic;
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clk: in std_ulogic;
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rst: in std_ulogic;
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rst: in std_ulogic;
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|
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mem_addr_16_1: in std_ulogic_vector(16 downto 1);
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mem_addr_16_1: in std_ulogic_vector(16 downto 2);
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mem_addr_16_1_we: in std_ulogic;
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mem_addr_16_1_we: in std_ulogic;
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mem_addr_26_17: in std_ulogic_vector(26 downto 17);
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mem_addr_26_17: in std_ulogic_vector(26 downto 17);
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mem_addr_26_17_we: in std_ulogic;
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mem_addr_26_17_we: in std_ulogic;
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mem_control_i: in std_ulogic_vector(5 downto 0);
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mem_control_i: in std_ulogic_vector(5 downto 0);
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mem_control_we: in std_ulogic;
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mem_control_we: in std_ulogic;
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mem_data_i: in std_ulogic_vector(15 downto 0);
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mem_data_i: in std_ulogic_vector(15 downto 0);
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mem_data_i_we: in std_ulogic;
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mem_data_i_we: in std_ulogic;
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|
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mem_data_o: out std_ulogic_vector(15 downto 0);
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mem_data_o: out std_ulogic_vector(15 downto 0);
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|
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RamCS: out std_ulogic := '1';
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ram_cs: out std_ulogic := '1';
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|
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MemOE: out std_ulogic := '0'; -- negative logic
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mem_oe: out std_ulogic := '0'; -- negative logic
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MemWR: out std_ulogic := '0'; -- negative logic
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mem_wr: out std_ulogic := '0'; -- negative logic
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MemAdv: out std_ulogic := '0'; -- negative logic
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mem_adv: out std_ulogic := '0'; -- negative logic
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MemWait: out std_ulogic := '0'; -- positive!
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mem_wait: out std_ulogic := '0'; -- positive!
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|
|
FlashCS: out std_ulogic := '0';
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flash_cs: out std_ulogic := '0';
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FlashRp: out std_ulogic := '1';
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flash_rp: out std_ulogic := '1';
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MemAdr: out std_ulogic_vector(26 downto 1) := (others => '0');
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mem_addr: out std_ulogic_vector(26 downto 1) := (others => '0');
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MemDB: inout std_logic_vector(15 downto 0) := (others => 'Z'));
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mem_data: inout std_logic_vector(15 downto 0) := (others => 'Z'));
|
end entity;
|
end entity;
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|
|
architecture rtl of ram_interface is
|
architecture rtl of ram_interface is
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signal mem_data_buf_i: std_ulogic_vector(mem_data_i'range) := (others => '0');
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signal mem_data_buf_i: std_ulogic_vector(mem_data_i'range) := (others => '0');
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signal mem_control_o: std_ulogic_vector(mem_control_i'range) := (others => '0');
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signal mem_control_o: std_ulogic_vector(mem_control_i'range) := (others => '0');
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signal mem_we: std_ulogic := '0';
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signal mem_we: std_ulogic := '0';
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signal mem_oe: std_ulogic := '0';
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signal mem_oe_internal: std_ulogic := '0';
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signal mem_addr_low: std_ulogic_vector(mem_addr_16_1'range) := (others => '0');
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signal mem_addr_low: std_ulogic_vector(mem_addr_16_1'range) := (others => '0');
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signal mem_addr_high: std_ulogic_vector(mem_addr_26_17'range) := (others => '0');
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signal mem_addr_high: std_ulogic_vector(mem_addr_26_17'range) := (others => '0');
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begin
|
begin
|
MemAdr <= '0' & mem_addr_high & mem_addr_low(mem_addr_low'high downto mem_addr_low'low + 1);
|
mem_addr <= '0' & mem_addr_high & mem_addr_low;
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|
|
mem_addr_16_1_reg: entity work.reg
|
mem_addr_16_1_reg: entity work.reg
|
generic map(N => mem_addr_16_1'length)
|
generic map(g => g, N => mem_addr_16_1'length)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
we => mem_addr_16_1_we,
|
we => mem_addr_16_1_we,
|
di => mem_addr_16_1,
|
di => mem_addr_16_1,
|
do => mem_addr_low);
|
do => mem_addr_low);
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|
|
mem_addr_26_17_reg: entity work.reg
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mem_addr_26_17_reg: entity work.reg
|
generic map(N => 10)
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generic map(g => g, N => mem_addr_26_17'length)
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port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
we => mem_addr_26_17_we,
|
we => mem_addr_26_17_we,
|
di => mem_addr_26_17,
|
di => mem_addr_26_17,
|
do => mem_addr_high);
|
do => mem_addr_high);
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|
|
mem_control_reg: entity work.reg
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mem_control_reg: entity work.reg
|
generic map(N => 6)
|
generic map(g => g, N => mem_control_i'length)
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port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
we => mem_control_we,
|
we => mem_control_we,
|
di => mem_control_i,
|
di => mem_control_i,
|
do => mem_control_o);
|
do => mem_control_o);
|
|
|
mem_data_i_reg: entity work.reg
|
mem_data_i_reg: entity work.reg
|
generic map(N => mem_data_i'length)
|
generic map(g => g, N => mem_data_i'length)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
we => mem_data_i_we,
|
we => mem_data_i_we,
|
di => mem_data_i,
|
di => mem_data_i,
|
do => mem_data_buf_i);
|
do => mem_data_buf_i);
|
|
|
FlashCS <= '0' when mem_control_o(5 downto 4) /= "00" and mem_control_o(0) = '1' else '1';
|
flash_cs <= '0' when mem_control_o(5 downto 4) /= "00" and mem_control_o(0) = '1' else '1' after g.delay;
|
RamCS <= '0' when mem_control_o(5 downto 4) /= "00" and mem_control_o(1) = '1' else '1';
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ram_cs <= '0' when mem_control_o(5 downto 4) /= "00" and mem_control_o(1) = '1' else '1' after g.delay;
|
MemWait <= mem_control_o(2);
|
mem_wait <= mem_control_o(2);
|
FlashRp <= '0' when mem_control_o(3) = '1' else '1';
|
flash_rp <= '0' when mem_control_o(3) = '1' else '1' after g.delay;
|
MemAdv <= '0' when mem_oe = '1' or mem_we = '1' else '1';
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mem_adv <= '0' when mem_oe_internal = '1' or mem_we = '1' else '1' after g.delay;
|
mem_oe <= '1' when mem_control_o(5 downto 4) = "01" else '0';
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mem_oe_internal <= '1' when mem_control_o(5 downto 4) = "01" else '0' after g.delay;
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mem_we <= '1' when mem_control_o(5 downto 4) = "10" else '0';
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mem_we <= '1' when mem_control_o(5 downto 4) = "10" else '0' after g.delay;
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|
|
MemOE <= not mem_oe;
|
mem_oe <= not mem_oe_internal after g.delay;
|
MemWR <= not mem_we;
|
mem_wr <= not mem_we after g.delay;
|
|
|
mem_data_o <= std_ulogic_vector(MemDB) when mem_oe = '1' else (others => '0');
|
mem_data_o <= std_ulogic_vector(mem_data) when mem_oe_internal = '1' else (others => '0') after g.delay;
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MemDB <= std_logic_vector(mem_data_buf_i) when mem_we = '1' else (others => 'Z');
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mem_data <= std_logic_vector(mem_data_buf_i) when mem_we = '1' else (others => 'Z') after g.delay;
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|
|
end architecture;
|
end architecture;
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No newline at end of file
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No newline at end of file
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