| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--| @file tb.vhd
|
--| @file tb.vhd
|
--| @brief Main test bench.
|
--| @brief Main test bench.
|
--|
|
--|
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--| @author Richard James Howe.
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--| @author Richard James Howe.
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--| @copyright Copyright 2013,2017 Richard James Howe.
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--| @copyright Copyright 2013-2019 Richard James Howe.
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--| @license MIT
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--| @license MIT
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--| @email howe.r.j.89@gmail.com
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--| @email howe.r.j.89@gmail.com
|
--|
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--|
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--| This test bench does quite a lot. It is not like normal VHDL test benches
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--| This test bench does quite a lot. It is not like normal VHDL test benches
|
--| in the fact that it uses configurable variables that it read in from a
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--| in the fact that it uses configurable variables that it reads in from a
|
--| file, which it does in an awkward but usable fashion.
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--| file, which it does in an awkward but usable fashion. It also has a
|
|
--| partially working way of connecting a simulated UART to STDIN/STDOUT, which
|
|
--| is a work in progress.
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--|
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--|
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--| It also tests multiple modules.
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--| It also tests multiple modules.
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--|
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--|
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--| @todo Optionally, read in from standard input and send the character
|
|
--| over the UART, then print out any received characters to standard out.
|
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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|
|
library ieee,work;
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library ieee,work;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use ieee.math_real.all;
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use std.textio.all;
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use std.textio.all;
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use work.util.all;
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use work.util.all;
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use work.core_pkg.all;
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use work.core_pkg.all;
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use work.vga_pkg.all;
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use work.vga_pkg.all;
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use work.uart_pkg.uart_core;
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|
|
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entity tb is
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entity tb is
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end tb;
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end tb;
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|
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architecture testing of tb is
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architecture testing of tb is
|
constant clock_frequency: positive := 100_000_000;
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constant g: common_generics := (
|
|
clock_frequency => 100_000_000,
|
|
asynchronous_reset => true,
|
|
delay => 0 ns);
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|
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constant number_of_interrupts: positive := 8;
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constant number_of_interrupts: positive := 8;
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constant uart_baud_rate: positive := 115200;
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constant uart_baud: positive := 115200;
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constant configuration_file_name: string := "tb.cfg";
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constant configuration_file_name: string := "tb.cfg";
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constant clk_period: time := 1000 ms / clock_frequency;
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constant uart_tx_time: time := (10*1000 ms) / 115200;
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constant uart_tx_time: time := (10*1000 ms) / 115200;
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constant uart_default_input: std_ulogic_vector(7 downto 0) := x"AA";
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constant reset_period_us: natural := 1;
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constant jitter_on: boolean := false;
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constant clock_period: time := 1000 ms / g.clock_frequency;
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constant tb_vga_on: boolean := false;
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constant tb_uart_on: boolean := false;
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constant tb_util_on: boolean := false;
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|
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-- Test bench configurable options --
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-- Test bench configurable options --
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|
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type configurable_items is record
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type configurable_items is record
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number_of_iterations: positive;
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number_of_iterations: natural; -- 0 == loop forever
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verbose: boolean;
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verbose: boolean;
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report_number: natural;
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report_number: natural;
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interactive: boolean;
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interactive: boolean;
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|
input_wait_for: time;
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end record;
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end record;
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|
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function set_configuration_items(ci: configuration_items) return configurable_items is
|
function set_configuration_items(ci: configuration_items) return configurable_items is
|
variable r: configurable_items;
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variable r: configurable_items;
|
begin
|
begin
|
r.number_of_iterations := ci(0).value;
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r.number_of_iterations := ci(0).value;
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r.verbose := ci(1).value > 0;
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r.verbose := ci(1).value > 0;
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r.interactive := ci(2).value > 0;
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r.interactive := ci(2).value > 0;
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r.report_number := ci(3).value;
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r.input_wait_for := ci(3).value * 1 ms;
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|
r.report_number := ci(4).value;
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return r;
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return r;
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end function;
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end function;
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|
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constant configuration_default: configuration_items(0 to 3) := (
|
constant configuration_default: configuration_items(0 to 4) := (
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(name => "Cycles ", value => 1000),
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(name => "Cycles ", value => 1000),
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(name => "Verbose ", value => 1),
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(name => "Verbose ", value => 1),
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(name => "Interact", value => 0),
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(name => "Interact", value => 0),
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(name => "InWaitMs", value => 8),
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(name => "LogFor ", value => 256));
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(name => "LogFor ", value => 256));
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|
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-- Test bench configurable options --
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-- Test bench configurable options --
|
|
|
signal stop: std_ulogic := '0';
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signal stop: boolean := false;
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signal debug: cpu_debug_interface;
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signal dbgi: cpu_debug_interface;
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|
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signal clk: std_ulogic := '0';
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signal clk: std_ulogic := '0';
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signal rst: std_ulogic := '0';
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signal rst: std_ulogic := '0';
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|
|
-- signal cpu_wait: std_ulogic := '0'; -- CPU wait flag
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|
|
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-- Basic I/O
|
-- Basic I/O
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signal btnu: std_ulogic := '0'; -- button up
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signal btnu: std_ulogic := '0'; -- button up
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signal btnd: std_ulogic := '0'; -- button down
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signal btnd: std_ulogic := '0'; -- button down
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signal btnc: std_ulogic := '0'; -- button centre
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signal btnc: std_ulogic := '0'; -- button centre
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signal btnl: std_ulogic := '0'; -- button left
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signal btnl: std_ulogic := '0'; -- button left
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| Line 106... |
Line 116... |
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shared variable cfg: configurable_items := set_configuration_items(configuration_default);
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shared variable cfg: configurable_items := set_configuration_items(configuration_default);
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|
|
signal configured: boolean := false;
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signal configured: boolean := false;
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|
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signal RamCS: std_ulogic := 'X';
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signal ram_cs: std_ulogic := 'X';
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signal MemOE: std_ulogic := 'X'; -- negative logic
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signal mem_oe: std_ulogic := 'X'; -- negative logic
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signal MemWR: std_ulogic := 'X'; -- negative logic
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signal mem_wr: std_ulogic := 'X'; -- negative logic
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signal MemAdv: std_ulogic := 'X'; -- negative logic
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signal mem_adv: std_ulogic := 'X'; -- negative logic
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signal MemWait: std_ulogic := 'X'; -- positive!
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signal mem_wait: std_ulogic := 'X'; -- positive!
|
signal FlashCS: std_ulogic := 'X';
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signal flash_cs: std_ulogic := 'X';
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signal FlashRp: std_ulogic := 'X';
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signal flash_rp: std_ulogic := 'X';
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signal MemAdr: std_ulogic_vector(26 downto 1) := (others => 'X');
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signal mem_addr: std_ulogic_vector(26 downto 1) := (others => 'X');
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signal MemDB: std_logic_vector(15 downto 0) := (others => 'X');
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signal mem_data: std_logic_vector(15 downto 0) := (others => 'X');
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|
|
begin
|
begin
|
---- Units under test ----------------------------------------------------------
|
---- Units under test ----------------------------------------------------------
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|
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MemDB <= (others => '0') when MemOE = '1' else (others => 'Z');
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mem_data <= (others => '0') when mem_oe = '1' else (others => 'Z');
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|
|
uut: entity work.top
|
uut: entity work.top
|
generic map(
|
generic map(
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clock_frequency => clock_frequency,
|
g => g,
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uart_baud_rate => uart_baud_rate)
|
reset_period_us => reset_period_us,
|
|
uart_baud => uart_baud)
|
port map(
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port map(
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debug => debug,
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debug => dbgi,
|
clk => clk,
|
clk => clk,
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-- rst => rst,
|
-- rst => rst,
|
btnu => btnu,
|
btnu => btnu,
|
btnd => btnd,
|
btnd => btnd,
|
btnc => btnc,
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btnc => btnc,
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| Line 145... |
Line 156... |
o_vga => o_vga,
|
o_vga => o_vga,
|
|
|
ps2_keyboard_data => ps2_keyboard_data,
|
ps2_keyboard_data => ps2_keyboard_data,
|
ps2_keyboard_clk => ps2_keyboard_clk,
|
ps2_keyboard_clk => ps2_keyboard_clk,
|
|
|
RamCS => RamCS,
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ram_cs => ram_cs,
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MemOE => MemOE,
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mem_oe => mem_oe,
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MemWR => MemWR,
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mem_wr => mem_wr,
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MemAdv => MemAdv,
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mem_adv => mem_adv,
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MemWait => MemWait,
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mem_wait => mem_wait,
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FlashCS => FlashCS,
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flash_cs => flash_cs,
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FlashRp => FlashRp,
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flash_rp => flash_rp,
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MemAdr => MemAdr,
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mem_addr => mem_addr,
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MemDB => MemDB);
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mem_data => mem_data);
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|
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uut_util: work.util.util_tb generic map(clock_frequency => clock_frequency);
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-- NB. It would be nice to configure these as off/on, as well as
|
uut_vga: work.vga_pkg.vt100_tb generic map(clock_frequency => clock_frequency);
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-- controlling how long they run for from here.
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util_g: if tb_util_on generate uut_util: work.util.util_tb generic map(g => g); end generate;
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-- The "io_pins_tb" works correctly, however GHDL 0.29, compiled under
|
vga_g: if tb_vga_on generate uut_vga: work.vga_pkg.vt100_tb generic map(g => g); end generate;
|
-- Windows, cannot fails to simulate this component correctly, and it
|
uart_g: if tb_uart_on generate uut_uart: work.uart_pkg.uart_tb generic map(g => g); end generate;
|
-- crashes. This does not affect the Linux build of GHDL. It has
|
|
-- something to do with 'Z' values for std_ulogic types.
|
uart_0_blk: block
|
--
|
signal uart_clock_rx_we, uart_clock_tx_we, uart_control_we: std_ulogic := '0';
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|
signal uart_reg: std_ulogic_vector(15 downto 0);
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uut_io_pins: work.util.io_pins_tb generic map(clock_frequency => clock_frequency);
|
begin
|
|
uart_0: work.uart_pkg.uart_core
|
uut_uart: work.uart_pkg.uart_core
|
generic map (g => g, baud => uart_baud)
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generic map(
|
|
baud_rate => uart_baud_rate,
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clock_frequency => clock_frequency)
|
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
din => din,
|
tx_di => din,
|
din_stb => din_stb,
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tx_we => din_stb,
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din_ack => din_ack,
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tx_ok => din_ack,
|
tx => rx,
|
tx => rx,
|
|
|
rx => tx,
|
rx => tx,
|
dout_ack => dout_ack,
|
rx_ok => open,
|
dout_stb => dout_stb,
|
rx_nd => dout_stb,
|
dout => dout);
|
rx_do => dout,
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rx_re => dout_ack,
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|
|
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reg => uart_reg,
|
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clock_reg_tx_we => uart_clock_tx_we,
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clock_reg_rx_we => uart_clock_rx_we,
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control_reg_we => uart_control_we);
|
|
end block;
|
|
|
------ Simulation only processes ----------------------------------------------
|
------ Simulation only processes ----------------------------------------------
|
clk_process: process
|
clk_process: process
|
|
variable seed1, seed2 : positive;
|
|
variable r : real;
|
|
variable jit_high, jit_low: time := 0 ns;
|
begin
|
begin
|
while stop = '0' loop
|
while not stop loop
|
|
if jitter_on then
|
|
uniform(seed1, seed2, r);
|
|
jit_high := r * g.delay;
|
|
uniform(seed1, seed2, r);
|
|
jit_low := r * g.delay;
|
|
uniform(seed1, seed2, r);
|
|
if r < 0.5 then jit_high := -jit_high; end if;
|
|
uniform(seed1, seed2, r);
|
|
if r < 0.5 then jit_low := -jit_low; end if;
|
|
else
|
|
jit_high := 0 ns;
|
|
jit_low := 0 ns;
|
|
end if;
|
clk <= '1';
|
clk <= '1';
|
wait for clk_period / 2;
|
wait for (clock_period / 2) + jit_high;
|
clk <= '0';
|
clk <= '0';
|
wait for clk_period / 2;
|
wait for (clock_period / 2) + jit_low;
|
end loop;
|
end loop;
|
|
report "clk_process end";
|
wait;
|
wait;
|
end process;
|
end process;
|
|
|
output_process: process
|
output_process: process
|
variable oline: line;
|
variable oline: line;
|
| Line 202... |
Line 235... |
variable have_char: boolean := true;
|
variable have_char: boolean := true;
|
begin
|
begin
|
wait until configured;
|
wait until configured;
|
|
|
if not cfg.interactive then
|
if not cfg.interactive then
|
|
report "Output turned off";
|
|
report "output_process end";
|
wait;
|
wait;
|
end if;
|
end if;
|
|
|
report "WRITING TO STDOUT";
|
report "Writing to STDOUT";
|
while stop = '0' loop
|
while not stop loop
|
wait until (dout_stb = '1' or stop = '1');
|
wait until (dout_stb = '1' or stop);
|
if stop = '0' then
|
if not stop then
|
c := character'val(to_integer(unsigned(dout)));
|
c := character'val(to_integer(unsigned(dout)));
|
write(oline, c);
|
write(oline, c);
|
have_char := true;
|
have_char := true;
|
if dout = x"0d" then
|
if dout = x"0d" then
|
writeline(output, oline);
|
writeline(output, oline);
|
have_char := false;
|
have_char := false;
|
end if;
|
end if;
|
wait for clk_period;
|
wait for clock_period;
|
dout_ack <= '1';
|
dout_ack <= '1';
|
wait for clk_period;
|
wait for clock_period;
|
dout_ack <= '0';
|
dout_ack <= '0';
|
end if;
|
end if;
|
end loop;
|
end loop;
|
if have_char then
|
if have_char then
|
writeline(output, oline);
|
writeline(output, oline);
|
end if;
|
end if;
|
|
report "output_process end";
|
wait;
|
wait;
|
end process;
|
end process;
|
|
|
|
|
-- @note The Input and Output mechanism that allows the tester to
|
-- The Input and Output mechanism that allows the tester to
|
-- interact with the running simulation needs more work, it is buggy
|
-- interact with the running simulation needs more work, it is buggy
|
-- and experimental, but demonstrates the principle - that a VHDL
|
-- and experimental, but demonstrates the principle - that a VHDL
|
-- test bench can be interacted with at run time.
|
-- test bench can be interacted with at run time.
|
input_process: process
|
input_process: process
|
variable c: character := ' ';
|
variable c: character := ' ';
|
variable iline: line;
|
variable iline: line;
|
-- variable oline: line;
|
-- variable oline: line;
|
variable good: boolean := true;
|
variable good: boolean := true;
|
|
variable eoi: boolean := false;
|
begin
|
begin
|
din_stb <= '0';
|
din_stb <= '0';
|
din <= x"00";
|
din <= x"00";
|
wait until configured;
|
wait until configured;
|
if not cfg.interactive then
|
if not cfg.interactive then
|
din_stb <= '1';
|
din_stb <= '1';
|
din <= x"AA";
|
din <= uart_default_input;
|
|
report "input process non-interactive";
|
|
report "input_process end";
|
wait;
|
wait;
|
end if;
|
end if;
|
|
|
report "READING FROM STDIN";
|
report "Waiting for " & time'image(cfg.input_wait_for) & " (before reading from STDIN)";
|
while (not endfile(input)) and stop = '0' loop
|
wait for cfg.input_wait_for;
|
|
report "Reading from STDIN (Hit EOF/CTRL-D/CTRL-Z After entering a line)";
|
|
while (not endfile(input)) and not stop and eoi = false loop
|
|
report "readline...";
|
readline(input, iline);
|
readline(input, iline);
|
good := true;
|
good := true;
|
while good and stop = '0' loop
|
while good and not stop loop
|
read(iline, c, good);
|
read(iline, c, good);
|
if good then
|
if good then
|
report "" & c;
|
report "" & c;
|
|
else
|
|
report "EOL/EOI";
|
|
c := LF;
|
|
eoi := true;
|
end if;
|
end if;
|
din <=
|
din <= std_ulogic_vector(to_unsigned(character'pos(c), din'length));
|
std_ulogic_vector(to_unsigned(character'pos(c), din'length));
|
|
din_stb <= '1';
|
din_stb <= '1';
|
wait for clk_period;
|
wait for clock_period;
|
din_stb <= '0';
|
din_stb <= '0';
|
assert din_ack = '1' severity warning;
|
wait for 100 us;
|
-- wait for 100 us;
|
|
wait for 10 ms;
|
|
end loop;
|
end loop;
|
end loop;
|
end loop;
|
-- stop <= '1';
|
report "input_process end";
|
wait;
|
wait;
|
end process;
|
end process;
|
|
|
hsync_gone_high <= true when o_vga.hsync = '1' else hsync_gone_high;
|
hsync_gone_high <= true when o_vga.hsync = '1' else hsync_gone_high;
|
vsync_gone_high <= true when o_vga.vsync = '1' else vsync_gone_high;
|
vsync_gone_high <= true when o_vga.vsync = '1' else vsync_gone_high;
|
| Line 315... |
Line 358... |
read_configuration_tb(configuration_file_name, configuration_values);
|
read_configuration_tb(configuration_file_name, configuration_values);
|
cfg := set_configuration_items(configuration_values);
|
cfg := set_configuration_items(configuration_values);
|
configured <= true;
|
configured <= true;
|
|
|
rst <= '1';
|
rst <= '1';
|
wait for clk_period * 2;
|
wait for clock_period * 2;
|
rst <= '0';
|
rst <= '0';
|
|
|
|
if cfg.number_of_iterations = 0 then
|
|
report "RUNNING FOREVER: number of iterations is zero" severity warning;
|
|
report "stimulus_process end";
|
|
wait;
|
|
end if;
|
|
|
for i in 0 to cfg.number_of_iterations loop
|
for i in 0 to cfg.number_of_iterations loop
|
if cfg.verbose then
|
if cfg.verbose then
|
if count < cfg.report_number then
|
if count < cfg.report_number then
|
w := reportln(debug, count);
|
w := reportln(dbgi, count);
|
writeline(OUTPUT, w);
|
writeline(OUTPUT, w);
|
count := count + 1;
|
count := count + 1;
|
elsif count < cfg.report_number + 1 then
|
elsif count < cfg.report_number + 1 then
|
report "Simulation continuing: Reporting turned off";
|
report "Simulation continuing: Reporting turned off";
|
count := count + 1;
|
count := count + 1;
|
end if;
|
end if;
|
end if;
|
end if;
|
wait for clk_period * 1;
|
wait for clock_period * 1;
|
end loop;
|
end loop;
|
|
|
|
-- These HSYNC and VSYNC asserts are included under the assumption
|
|
-- that the image running on the H2 CPU will initiate the VGA, if
|
|
-- it does not (perhaps because it is running it's own initialization
|
|
-- routines), then the HSYNC or VSYNC will never go high - so this is
|
|
-- not necessarily an error.
|
|
--
|
-- It would be nice to test the other peripherals as
|
-- It would be nice to test the other peripherals as
|
-- well, the CPU-ID should be written to the LED 7 Segment
|
-- well, the CPU-ID should be written to the LED 7 Segment
|
-- displays, however we only get the cathode and anode
|
-- displays, however we only get the cathode and anode
|
-- values out of the unit.
|
-- values out of the unit.
|
|
|
assert hsync_gone_high report "HSYNC not active - H2 failed to initialize VGA module";
|
assert hsync_gone_high report "HSYNC not active - H2 failed to initialize VGA module";
|
assert vsync_gone_high report "VSYNC not active - H2 failed to initialize VGA module";
|
assert vsync_gone_high report "VSYNC not active - H2 failed to initialize VGA module";
|
|
|
stop <= '1';
|
stop <= true;
|
|
report "stimulus_process end";
|
wait;
|
wait;
|
end process;
|
end process;
|
|
|
end architecture;
|
end architecture;
|
------ END ---------------------------------------------------------------------
|
------ END ---------------------------------------------------------------------
|
