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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee,work,std;
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library ieee,work,std;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.util.common_generics;
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entity timer is
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entity timer is
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generic(
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generic(
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g: common_generics;
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timer_length: positive := 16);
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timer_length: positive := 16);
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port(
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port(
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clk: in std_ulogic;
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clk: in std_ulogic;
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rst: in std_ulogic;
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rst: in std_ulogic;
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irq_en <= control_c(irq_enable_bit);
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irq_en <= control_c(irq_enable_bit);
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compare <= control_c(timer_highest_bit downto 0);
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compare <= control_c(timer_highest_bit downto 0);
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counter_o <= std_ulogic_vector(count);
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counter_o <= std_ulogic_vector(count);
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clockRegisters: process(clk, rst)
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begin
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if rst = '1' then
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control_c <= (others => '0');
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elsif rising_edge(clk) then
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control_c <= control_n;
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end if;
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end process;
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counter: process (clk, rst)
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counter: process (clk, rst)
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begin
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begin
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if rst = '1' then
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if rst = '1' and g.asynchronous_reset then
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count <= (others => '0');
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count <= (others => '0') after g.delay;
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control_c <= (others => '0') after g.delay;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if rst = '1' and not g.asynchronous_reset then
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count <= (others => '0') after g.delay;
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control_c <= (others => '0') after g.delay;
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else
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control_c <= control_n;
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if reset_timer = '1' or timer_reset = '1' then
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if reset_timer = '1' or timer_reset = '1' then
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count <= (others => '0');
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count <= (others => '0') after g.delay;
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elsif enabled = '1' then
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elsif enabled = '1' then
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count <= count + 1;
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count <= count + 1 after g.delay;
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else
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else
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count <= count;
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count <= count after g.delay;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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output: process(count, we, control_i, control_c, compare, irq_en, enabled)
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output: process(count, we, control_i, control_c, compare, irq_en, enabled)
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begin
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begin
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irq <= '0';
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control_n <= control_c;
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timer_reset <= '0';
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control_n(timer_reset_bit) <= '0'; -- reset
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if we = '1' then
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if we = '1' then
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control_n <= control_i;
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control_n <= control_i after g.delay;
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else
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control_n <= control_c after g.delay;
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control_n(timer_reset_bit) <= '0' after g.delay; -- reset
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end if;
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end if;
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if count = unsigned(compare) and enabled = '1' then
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if count = unsigned(compare) and enabled = '1' then
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if irq_en = '1' then
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irq <= irq_en after g.delay;
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irq <= '1';
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timer_reset <= '1' after g.delay;
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end if;
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else
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timer_reset <= '1';
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irq <= '0' after g.delay;
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timer_reset <= '0' after g.delay;
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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