| Line 14... |
Line 14... |
library ieee,work;
|
library ieee,work;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.core_pkg.all;
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use work.core_pkg.all;
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use work.vga_pkg.all;
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use work.vga_pkg.all;
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use work.led_pkg.all;
|
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use work.kbd_pkg.ps2_kbd_top;
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use work.kbd_pkg.ps2_kbd_top;
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use work.uart_pkg.uart_core;
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use work.util.all;
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use work.util.state_block_changed;
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use work.uart_pkg.all;
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|
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entity top is
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entity top is
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generic(
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generic(
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clock_frequency: positive := 100_000_000;
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g: common_generics := default_settings;
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uart_baud_rate: positive := 115200;
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reset_period_us: natural := 100;
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uart_baud: positive := 115200;
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uart_fifo_depth: positive := 8);
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uart_fifo_depth: positive := 8);
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port
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port
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(
|
(
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-- synthesis translate_off
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-- synthesis translate_off
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debug: out cpu_debug_interface;
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debug: out cpu_debug_interface;
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| Line 57... |
Line 57... |
-- PS/2 Interface
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-- PS/2 Interface
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ps2_keyboard_data: in std_ulogic := '0';
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ps2_keyboard_data: in std_ulogic := '0';
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ps2_keyboard_clk: in std_ulogic := '0';
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ps2_keyboard_clk: in std_ulogic := '0';
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|
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-- Memory Interface
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-- Memory Interface
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RamCS: out std_ulogic := '1';
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ram_cs: out std_ulogic := '1';
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MemOE: out std_ulogic := '0'; -- negative logic
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mem_oe: out std_ulogic := '0'; -- negative logic
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MemWR: out std_ulogic := '0'; -- negative logic
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mem_wr: out std_ulogic := '0'; -- negative logic
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MemAdv: out std_ulogic := '0'; -- negative logic
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mem_adv: out std_ulogic := '0'; -- negative logic
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MemWait: out std_ulogic := '0'; -- positive!
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mem_wait: out std_ulogic := '0'; -- positive logic!
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FlashCS: out std_ulogic := '0';
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flash_cs: out std_ulogic := '0';
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FlashRp: out std_ulogic := '1';
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flash_rp: out std_ulogic := '1';
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MemAdr: out std_ulogic_vector(26 downto 1) := (others => '0');
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mem_addr: out std_ulogic_vector(26 downto 1) := (others => '0');
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MemDB: inout std_logic_vector(15 downto 0) := (others => 'Z'));
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mem_data: inout std_logic_vector(15 downto 0) := (others => 'Z'));
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end;
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end;
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|
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architecture behav of top is
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architecture behav of top is
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constant timer_length: positive := 16;
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constant timer_length: positive := 16;
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constant number_of_interrupts: positive := 8;
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constant number_of_interrupts: positive := 8;
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constant number_of_led_displays: positive := 4;
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constant number_of_led_displays: positive := 4;
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constant timer_period_us: positive := 20000;
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constant timer_period_us: positive := 20000;
|
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constant use_sine: boolean := false;
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|
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-- Signals
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-- Signals
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signal rst: std_ulogic := '0';
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signal rst: std_ulogic := '0';
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-- CPU H2 IO interface signals.
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-- CPU H2 IO interface signals.
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signal cpu_wait: std_ulogic := '0';
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signal cpu_wait: std_ulogic := '0';
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| Line 85... |
Line 86... |
signal io_din: std_ulogic_vector(15 downto 0) := (others => '0');
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signal io_din: std_ulogic_vector(15 downto 0) := (others => '0');
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signal io_dout: std_ulogic_vector(15 downto 0) := (others => '0');
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signal io_dout: std_ulogic_vector(15 downto 0) := (others => '0');
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signal io_daddr: std_ulogic_vector(15 downto 0) := (others => '0');
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signal io_daddr: std_ulogic_vector(15 downto 0) := (others => '0');
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|
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-- CPU H2 Interrupts
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-- CPU H2 Interrupts
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signal cpu_irq: std_ulogic := '0';
|
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signal cpu_irc: std_ulogic_vector(number_of_interrupts - 1 downto 0) := (others => '0');
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signal cpu_irc: std_ulogic_vector(number_of_interrupts - 1 downto 0) := (others => '0');
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signal cpu_irc_mask_we: std_ulogic := '0';
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signal cpu_irc_mask_we: std_ulogic := '0';
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|
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signal clk25MHz: std_ulogic:= '0';
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signal clk25MHz: std_ulogic:= '0';
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signal clk50MHz: std_ulogic:= '0';
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signal clk50MHz: std_ulogic:= '0';
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| Line 108... |
Line 108... |
signal vga_data_we: std_ulogic := '0';
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signal vga_data_we: std_ulogic := '0';
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signal vga_data_busy: std_ulogic := '0';
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signal vga_data_busy: std_ulogic := '0';
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|
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---- UART
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---- UART
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signal rx_data: std_ulogic_vector(7 downto 0) := (others => '0');
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signal rx_data: std_ulogic_vector(7 downto 0) := (others => '0');
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signal rx_data_n: std_ulogic_vector(7 downto 0) := (others => '0');
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signal rx_fifo_empty: std_ulogic := '0';
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signal rx_fifo_empty: std_ulogic := '0';
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signal rx_fifo_full: std_ulogic := '0';
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signal rx_fifo_full: std_ulogic := '0';
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signal rx_data_re: std_ulogic := '0';
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signal rx_data_re: std_ulogic := '0';
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signal rx_data_re_n: std_ulogic := '0';
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|
|
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signal tx_data: std_ulogic_vector(7 downto 0) := (others => '0');
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signal tx_fifo_full: std_ulogic := '0';
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signal tx_fifo_full: std_ulogic := '0';
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signal tx_fifo_empty: std_ulogic := '0';
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signal tx_fifo_empty: std_ulogic := '0';
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signal tx_data_we: std_ulogic := '0';
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signal tx_data_we: std_ulogic := '0';
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|
|
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signal uart_clock_tx_we: std_ulogic := '0';
|
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signal uart_clock_rx_we: std_ulogic := '0';
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signal uart_control_we: std_ulogic := '0';
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---- Timer
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---- Timer
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signal timer_control_we: std_ulogic := '0';
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signal timer_control_we: std_ulogic := '0';
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signal timer_counter_o: std_ulogic_vector(timer_length - 4 downto 0) := (others =>'0');
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signal timer_counter_o: std_ulogic_vector(timer_length - 4 downto 0) := (others =>'0');
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signal timer_irq: std_ulogic;
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signal timer_irq: std_ulogic;
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|
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| Line 130... |
Line 130... |
signal kbd_char_buf_new: std_ulogic := '0';
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signal kbd_char_buf_new: std_ulogic := '0';
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signal kbd_char_buf: std_ulogic_vector(6 downto 0) := (others => '0'); -- ASCII char
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signal kbd_char_buf: std_ulogic_vector(6 downto 0) := (others => '0'); -- ASCII char
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signal kbd_char_re: std_ulogic := '0';
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signal kbd_char_re: std_ulogic := '0';
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|
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---- 8 Segment Display
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---- 8 Segment Display
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|
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signal leds_reg_we: std_ulogic := '0';
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signal leds_reg_we: std_ulogic := '0';
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|
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---- Buttons
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---- Buttons
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signal btnu_d: std_ulogic := '0'; -- button up
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signal btnu_d: std_ulogic := '0'; -- button up
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signal btnd_d: std_ulogic := '0'; -- button down
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signal btnd_d: std_ulogic := '0'; -- button down
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| Line 150... |
Line 149... |
signal mem_addr_26_17_we: std_ulogic := '0';
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signal mem_addr_26_17_we: std_ulogic := '0';
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signal mem_addr_16_1_we: std_ulogic := '0';
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signal mem_addr_16_1_we: std_ulogic := '0';
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signal mem_data_i_we: std_ulogic := '0';
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signal mem_data_i_we: std_ulogic := '0';
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signal mem_data_o: std_ulogic_vector(15 downto 0) := (others => '0');
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signal mem_data_o: std_ulogic_vector(15 downto 0) := (others => '0');
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signal mem_control_we: std_ulogic := '0';
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signal mem_control_we: std_ulogic := '0';
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signal mem_we: std_ulogic := '0';
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signal mem_oe: std_ulogic := '0';
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signal sine_we: std_ulogic := '0';
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signal sine: std_ulogic_vector(15 downto 0) := (others => '0');
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|
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begin
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begin
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- The Main components
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-- The Main components
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
|
|
------- Output assignments (Not in a process) ---------------------------------
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cpu_wait <= btnc_d; -- temporary testing measure only!
|
|
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-- @warning These are both temporary measures for testing only!
|
system_reset: work.util.reset_generator
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-- rst <= btnu_d;
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generic map (g => g, reset_period_us => reset_period_us)
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cpu_wait <= btnc_d;
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|
|
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irq_block: block
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signal rx_fifo_not_empty: std_ulogic := '0';
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signal tx_fifo_not_empty: std_ulogic := '0';
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|
|
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signal rx_fifo_not_empty_edge: std_ulogic := '0';
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signal rx_fifo_full_edge: std_ulogic := '0';
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signal tx_fifo_not_empty_edge: std_ulogic := '0';
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signal tx_fifo_full_edge: std_ulogic := '0';
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signal kbd_char_buf_new_edge: std_ulogic := '0';
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begin
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rx_fifo_not_empty <= not rx_fifo_empty;
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tx_fifo_not_empty <= not rx_fifo_empty;
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|
|
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-- @note It might be best to move this into the IRQ handler,
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-- to ensure all inputs are edge triggered.
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irq_edges: work.util.rising_edge_detectors
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generic map(N => 5)
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port map(
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port map(
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst);
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di(0) => rx_fifo_not_empty,
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di(1) => rx_fifo_full,
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-- NB. Video blanking interrupts would be useful for writing
|
di(2) => tx_fifo_not_empty,
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-- graphics code (if the VGA module had a graphics mode, which it
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di(3) => tx_fifo_full,
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-- currently does not).
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di(4) => kbd_char_buf_new,
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cpu_irc(0) <= btnu_d; -- configurable CPU reset (can mask this)
|
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cpu_irc(1) <= not rx_fifo_empty;
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do(0) => rx_fifo_not_empty_edge,
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cpu_irc(2) <= rx_fifo_full;
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do(1) => rx_fifo_full_edge,
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cpu_irc(3) <= not tx_fifo_empty;
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do(2) => tx_fifo_not_empty_edge,
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cpu_irc(4) <= tx_fifo_full;
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do(3) => tx_fifo_full_edge,
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cpu_irc(5) <= kbd_char_buf_new;
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do(4) => kbd_char_buf_new_edge);
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|
|
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cpu_irc(0) <= '0';
|
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cpu_irc(1) <= rx_fifo_not_empty_edge;
|
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cpu_irc(2) <= rx_fifo_full_edge;
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cpu_irc(3) <= tx_fifo_not_empty_edge;
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cpu_irc(4) <= tx_fifo_full_edge;
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cpu_irc(5) <= kbd_char_buf_new_edge;
|
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cpu_irc(6) <= timer_irq;
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cpu_irc(6) <= timer_irq;
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cpu_irc(7) <= button_changed;
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cpu_irc(7) <= button_changed;
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|
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cpu_irq <= '1' when
|
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timer_irq = '1' or
|
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rx_fifo_not_empty_edge = '1' or
|
|
rx_fifo_full_edge = '1' or
|
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tx_fifo_not_empty_edge = '1' or
|
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tx_fifo_full_edge = '1' or
|
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kbd_char_buf_new_edge = '1' or
|
|
button_changed = '1'
|
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else '0';
|
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end block;
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|
|
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core_0: entity work.core
|
core_0: entity work.core
|
generic map(number_of_interrupts => number_of_interrupts)
|
generic map (g => g, number_of_interrupts => number_of_interrupts)
|
port map(
|
port map(
|
-- synthesis translate_off
|
-- synthesis translate_off
|
debug => debug,
|
debug => debug,
|
-- synthesis translate_on
|
-- synthesis translate_on
|
clk => clk,
|
clk => clk,
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| Line 229... |
Line 192... |
io_wr => io_wr,
|
io_wr => io_wr,
|
io_re => io_re,
|
io_re => io_re,
|
io_din => io_din,
|
io_din => io_din,
|
io_dout => io_dout,
|
io_dout => io_dout,
|
io_daddr => io_daddr,
|
io_daddr => io_daddr,
|
cpu_irq => cpu_irq,
|
|
cpu_irc => cpu_irc,
|
cpu_irc => cpu_irc,
|
cpu_irc_mask => io_dout(number_of_interrupts - 1 downto 0),
|
cpu_irc_mask => io_dout(number_of_interrupts - 1 downto 0),
|
cpu_irc_mask_we => cpu_irc_mask_we);
|
cpu_irc_mask_we => cpu_irc_mask_we);
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- IO
|
-- IO
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
|
-- NOTE: A Wishbone Interface on each of the components would simplify the
|
|
-- system overall. However, each peripheral would need an interface
|
|
-- specifying. This module could be made to be much smaller.
|
|
-- See: <https://en.wikipedia.org/wiki/Wishbone_(computer_bus)>
|
|
-- And: <http://cdn.opencores.org/downloads/wbspec_b4.pdf>
|
|
|
-- Xilinx Application Note:
|
-- Xilinx Application Note:
|
-- It seems like it buffers the clock correctly here, so no need to
|
-- It seems like it buffers the clock correctly here, so no need to
|
-- use a DCM. However, see:
|
-- use a DCM. However, see:
|
-- http://electronics.stackexchange.com/questions/112534/using-digital-clock-manager-with-verilog-to-generate-25mhz-clock-from-32mhz-inte
|
-- http://electronics.stackexchange.com/questions/112534/using-digital-clock-manager-with-verilog-to-generate-25mhz-clock-from-32mhz-inte
|
---- Clock divider /2.
|
---- Clock divider /2.
|
clk50MHz <= '0' when rst = '1' else not clk50MHz when rising_edge(clk);
|
clk50MHz <= '0' when rst = '1' else not clk50MHz when rising_edge(clk);
|
|
|
---- Clock divider /2. Pixel clock is 25MHz
|
---- Clock divider /2. Pixel clock is 25MHz
|
clk25MHz <= '0' when rst = '1' else not clk25MHz when rising_edge(clk50MHz);
|
clk25MHz <= '0' when rst = '1' else not clk25MHz when rising_edge(clk50MHz);
|
|
|
|
-- It possible for CPU to issue both signals at the same time, but it should
|
|
-- not happen with a standard instruction.
|
assert not(io_wr = '1' and io_re = '1') report "IO Read/Write issued at same time" severity error;
|
assert not(io_wr = '1' and io_re = '1') report "IO Read/Write issued at same time" severity error;
|
-- assert not(io_wr = '1' or io_re = '1') or not io_daddr(0) = '1' report "Unaligned register access" severity error;
|
|
|
|
vga_data <= io_dout(vga_data'range);
|
vga_data <= io_dout(vga_data'range);
|
tx_data <= io_dout(tx_data'range);
|
|
|
|
io_write: block
|
io_write: block
|
signal selector: std_ulogic_vector(3 downto 0) := (others => '0');
|
signal selector: std_ulogic_vector(3 downto 0) := (others => '0');
|
signal is_write: boolean := false;
|
signal is_write: boolean := false;
|
begin
|
begin
|
| Line 277... |
Line 246... |
|
|
mem_addr_16_1_we <= '1' when is_write and selector = x"6" else '0';
|
mem_addr_16_1_we <= '1' when is_write and selector = x"6" else '0';
|
|
|
leds_reg_we <= '1' when is_write and selector = x"7" else '0';
|
leds_reg_we <= '1' when is_write and selector = x"7" else '0';
|
cpu_irc_mask_we <= '1' when is_write and selector = x"8" else '0';
|
cpu_irc_mask_we <= '1' when is_write and selector = x"8" else '0';
|
|
|
|
uart_clock_tx_we <= '1' when is_write and selector = x"9" else '0';
|
|
uart_clock_rx_we <= '1' when is_write and selector = x"A" else '0';
|
|
uart_control_we <= '1' when is_write and selector = x"B" else '0';
|
|
|
|
sine_o: if use_sine generate
|
|
sine_we <= '1' when is_write and selector = x"C" else '0';
|
|
end generate;
|
end block;
|
end block;
|
|
|
io_read: process(
|
io_read: process(
|
io_wr, io_re, io_daddr,
|
io_wr, io_re, io_daddr,
|
sw_d, btnu_d, btnd_d, btnl_d, btnr_d, btnc_d,
|
sw_d, btnu_d, btnd_d, btnl_d, btnr_d, btnc_d,
|
kbd_char_buf_new, kbd_char_buf,
|
kbd_char_buf_new, kbd_char_buf,
|
|
|
rx_data_n,
|
rx_data,
|
rx_fifo_empty,
|
rx_fifo_empty,
|
rx_fifo_full,
|
rx_fifo_full,
|
|
|
tx_fifo_full,
|
tx_fifo_full,
|
tx_fifo_empty,
|
tx_fifo_empty,
|
|
|
timer_counter_o,
|
timer_counter_o,
|
|
|
vga_data_busy,
|
vga_data_busy,
|
|
sine,
|
|
|
mem_data_o)
|
mem_data_o)
|
begin
|
begin
|
|
|
io_din <= (others => '0');
|
io_din <= (others => '0');
|
|
|
-- The signal io_re is not needed as none of the reads have
|
-- The signal io_re is not needed as none of the reads have
|
-- any side effects
|
-- any side effects
|
|
|
case io_daddr(3 downto 1) is
|
case io_daddr(3 downto 1) is
|
when "000" => -- buttons, plus direct access to UART bit.
|
when "000" => -- buttons, plus direct access to UART bit.
|
io_din(7 downto 0) <= rx_data_n;
|
io_din(7 downto 0) <= rx_data;
|
io_din(8) <= rx_fifo_empty;
|
io_din(8) <= rx_fifo_empty;
|
io_din(9) <= rx_fifo_full;
|
io_din(9) <= rx_fifo_full;
|
io_din(11) <= tx_fifo_empty;
|
io_din(11) <= tx_fifo_empty;
|
io_din(12) <= tx_fifo_full;
|
io_din(12) <= tx_fifo_full;
|
when "001" => -- VT100 status and Keyboard
|
when "001" => -- VT100 status and Keyboard
|
| Line 321... |
Line 299... |
io_din(timer_counter_o'range) <= timer_counter_o;
|
io_din(timer_counter_o'range) <= timer_counter_o;
|
when "011" => -- Switches and buttons
|
when "011" => -- Switches and buttons
|
io_din <= "000" & btnu_d & btnd_d & btnl_d & btnr_d & btnc_d & sw_d;
|
io_din <= "000" & btnu_d & btnd_d & btnl_d & btnr_d & btnc_d & sw_d;
|
when "100" =>
|
when "100" =>
|
io_din <= mem_data_o;
|
io_din <= mem_data_o;
|
|
when "101" =>
|
|
if use_sine then
|
|
io_din <= sine;
|
|
end if;
|
when others => io_din <= (others => '0');
|
when others => io_din <= (others => '0');
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
--- UART ----------------------------------------------------------
|
--- Sine ----------------------------------------------------------
|
-- @todo Move registers inside UART module
|
sine_gen_0: if use_sine generate
|
uart_rx_data_reg_we_0: work.util.reg
|
sine_0: work.util.sine
|
generic map(
|
generic map(g => g)
|
N => 1)
|
port map(clk => clk, rst => rst, xwe => sine_we, x => io_dout, s => sine);
|
port map(
|
end generate;
|
clk => clk,
|
--- Sine ----------------------------------------------------------
|
rst => rst,
|
|
we => '1',
|
|
di(0) => rx_data_re,
|
|
do(0) => rx_data_re_n);
|
|
|
|
uart_rx_data_reg_0: work.util.reg
|
--- UART ----------------------------------------------------------
|
generic map(
|
uart_fifo_0: work.uart_pkg.uart_top
|
N => rx_data_n'high + 1)
|
generic map (g => g, baud => uart_baud, use_fifo => true)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
we => rx_data_re_n,
|
|
di => rx_data,
|
|
do => rx_data_n);
|
|
|
|
uart_0: work.uart_pkg.uart_top
|
tx => tx,
|
generic map(
|
|
baud_rate => uart_baud_rate,
|
|
clock_frequency => clock_frequency,
|
|
fifo_depth => uart_fifo_depth)
|
|
port map(
|
|
clk => clk,
|
|
rst => rst,
|
|
rx_data => rx_data,
|
|
rx_fifo_empty => rx_fifo_empty,
|
|
rx_fifo_full => rx_fifo_full,
|
|
rx_data_re => rx_data_re,
|
|
tx_data => tx_data,
|
|
tx_fifo_full => tx_fifo_full,
|
tx_fifo_full => tx_fifo_full,
|
tx_fifo_empty => tx_fifo_empty,
|
tx_fifo_empty => tx_fifo_empty,
|
tx_data_we => tx_data_we,
|
tx_fifo_we => tx_data_we,
|
tx => tx,
|
tx_fifo_data => io_dout(7 downto 0),
|
rx => rx);
|
|
|
rx => rx,
|
|
rx_fifo_re => rx_data_re,
|
|
rx_fifo_data => rx_data,
|
|
rx_fifo_full => rx_fifo_full,
|
|
rx_fifo_empty => rx_fifo_empty,
|
|
|
|
reg => io_dout,
|
|
clock_reg_tx_we => uart_clock_tx_we,
|
|
clock_reg_rx_we => uart_clock_rx_we,
|
|
control_reg_we => uart_control_we);
|
--- UART ----------------------------------------------------------
|
--- UART ----------------------------------------------------------
|
|
|
--- LED Output ----------------------------------------------------
|
--- LED Output ----------------------------------------------------
|
led_output_reg_0: entity work.reg
|
led_output_reg_0: entity work.reg
|
generic map(N => ld'high + 1)
|
generic map (g => g, N => ld'length)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
we => ld_we,
|
we => ld_we,
|
di => io_dout(ld'range),
|
di => io_dout(ld'range),
|
do => ld);
|
do => ld);
|
--- LED Output ----------------------------------------------------
|
--- LED Output ----------------------------------------------------
|
|
|
--- Timer ---------------------------------------------------------
|
--- Timer ---------------------------------------------------------
|
timer_0: entity work.timer
|
timer_0: entity work.timer
|
generic map(timer_length => timer_length)
|
generic map (g => g, timer_length => timer_length)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
we => timer_control_we,
|
we => timer_control_we,
|
control_i => io_dout,
|
control_i => io_dout,
|
counter_o => timer_counter_o,
|
counter_o => timer_counter_o,
|
irq => timer_irq);
|
irq => timer_irq);
|
--- Timer ---------------------------------------------------------
|
--- Timer ---------------------------------------------------------
|
|
|
--- VGA -----------------------------------------------------------
|
--- VGA -----------------------------------------------------------
|
|
vga_selector: block
|
|
constant use_vt100: boolean := true;
|
|
begin
|
|
gen_vt100_0: if use_vt100 generate
|
vt100_0: work.vga_pkg.vt100
|
vt100_0: work.vga_pkg.vt100
|
|
generic map (g => g)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
clk25MHz => clk25MHz,
|
clk25MHz => clk25MHz,
|
rst => rst,
|
rst => rst,
|
we => vga_data_we,
|
we => vga_data_we,
|
char => vga_data,
|
char => vga_data,
|
busy => vga_data_busy,
|
busy => vga_data_busy,
|
o_vga => o_vga);
|
o_vga => o_vga);
|
|
end generate;
|
|
|
|
-- Test code
|
|
-- NOTE: Timing is not the best, VGA monitor loses synchronization
|
|
-- every so often with this module.
|
|
vga_gen_c1: if not use_vt100 generate
|
|
vga_c1: block
|
|
signal row, column: integer := 0;
|
|
signal h_blank, v_blank, draw: std_ulogic := '0';
|
|
begin
|
|
draw <= not h_blank and not v_blank;
|
|
vga_c: work.util.vga_controller
|
|
generic map (
|
|
g => g,
|
|
pixel_clock_frequency => 25_000_000,
|
|
cfg => work.util.vga_640x480)
|
|
port map (
|
|
clk => clk25MHz,
|
|
rst => rst,
|
|
row => row,
|
|
column => column,
|
|
h_blank => h_blank,
|
|
v_blank => v_blank,
|
|
h_sync => o_vga.hsync,
|
|
v_sync => o_vga.vsync);
|
|
o_vga.red <= "111" when draw = '1' else "000";
|
|
o_vga.green <= "111" when (draw = '1' and row < 100 and column < 100) else "000";
|
|
o_vga.blue <= "11";
|
|
end block;
|
|
end generate;
|
|
end block;
|
--- VGA -----------------------------------------------------------
|
--- VGA -----------------------------------------------------------
|
|
|
--- Keyboard ------------------------------------------------------
|
--- Keyboard ------------------------------------------------------
|
keyboard_0: work.kbd_pkg.keyboard
|
keyboard_0: work.kbd_pkg.keyboard
|
generic map(
|
generic map (g => g, ps2_debounce_counter_size => 8)
|
clock_frequency => clock_frequency,
|
|
ps2_debounce_counter_size => 8)
|
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
|
|
ps2_clk => ps2_keyboard_clk,
|
ps2_clk => ps2_keyboard_clk,
|
| Line 420... |
Line 427... |
kbd_char_buf_new => kbd_char_buf_new,
|
kbd_char_buf_new => kbd_char_buf_new,
|
kbd_char_buf => kbd_char_buf);
|
kbd_char_buf => kbd_char_buf);
|
--- Keyboard ------------------------------------------------------
|
--- Keyboard ------------------------------------------------------
|
|
|
--- LED 8 Segment display -----------------------------------------
|
--- LED 8 Segment display -----------------------------------------
|
ledseg_0: entity work.led_8_segment_display
|
ledseg_0: entity work.led_7_segment_display
|
generic map(
|
generic map(
|
|
g => g,
|
number_of_led_displays => number_of_led_displays,
|
number_of_led_displays => number_of_led_displays,
|
clock_frequency => clock_frequency,
|
|
use_bcd_not_hex => false)
|
use_bcd_not_hex => false)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
|
|
| Line 438... |
Line 445... |
ka => ka);
|
ka => ka);
|
--- LED 8 Segment display -----------------------------------------
|
--- LED 8 Segment display -----------------------------------------
|
|
|
--- Buttons -------------------------------------------------------
|
--- Buttons -------------------------------------------------------
|
button_debouncer: work.util.debounce_block_us
|
button_debouncer: work.util.debounce_block_us
|
generic map(
|
generic map (g => g, N => 5, timer_period_us => timer_period_us)
|
N => 5,
|
|
clock_frequency => clock_frequency,
|
|
timer_period_us => timer_period_us)
|
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
di(0) => btnu,
|
di(0) => btnu,
|
di(1) => btnd,
|
di(1) => btnd,
|
di(2) => btnc,
|
di(2) => btnc,
|
| Line 460... |
Line 464... |
dpad_changed: block
|
dpad_changed: block
|
signal changed_signals: std_ulogic_vector(4 downto 0) := (others => '0');
|
signal changed_signals: std_ulogic_vector(4 downto 0) := (others => '0');
|
signal any_changed_signals: std_ulogic := '0';
|
signal any_changed_signals: std_ulogic := '0';
|
begin
|
begin
|
state_changed: work.util.state_block_changed
|
state_changed: work.util.state_block_changed
|
generic map(N => changed_signals'length)
|
generic map (g => g, N => changed_signals'length)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
di(0) => btnu_d,
|
di(0) => btnu_d,
|
di(1) => btnd_d,
|
di(1) => btnd_d,
|
| Line 474... |
Line 478... |
do => changed_signals);
|
do => changed_signals);
|
|
|
any_changed_signals <= '1' when changed_signals /= "00000" else '0';
|
any_changed_signals <= '1' when changed_signals /= "00000" else '0';
|
|
|
state_changed_reg: work.util.reg
|
state_changed_reg: work.util.reg
|
generic map(N => 1)
|
generic map (g => g, N => 1)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
di(0) => any_changed_signals,
|
di(0) => any_changed_signals,
|
we => '1',
|
we => '1',
|
| Line 487... |
Line 491... |
|
|
--- Buttons -------------------------------------------------------
|
--- Buttons -------------------------------------------------------
|
|
|
--- Switches ------------------------------------------------------
|
--- Switches ------------------------------------------------------
|
sw_debouncer: work.util.debounce_block_us
|
sw_debouncer: work.util.debounce_block_us
|
generic map(
|
generic map (g => g, N => sw'length, timer_period_us => timer_period_us)
|
N => sw'high+1,
|
|
clock_frequency => clock_frequency,
|
|
timer_period_us => timer_period_us)
|
|
port map(clk => clk, di => sw, do => sw_d);
|
port map(clk => clk, di => sw, do => sw_d);
|
--- Switches ------------------------------------------------------
|
--- Switches ------------------------------------------------------
|
|
|
--- Memory Interface ----------------------------------------------
|
--- Memory Interface ----------------------------------------------
|
ram_interface_0: entity work.ram_interface
|
ram_interface_0: entity work.ram_interface
|
|
generic map (g => g)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
mem_addr_16_1 => io_dout,
|
mem_addr_16_1 => io_dout(io_dout'high downto 1),
|
mem_addr_16_1_we => mem_addr_16_1_we,
|
mem_addr_16_1_we => mem_addr_16_1_we,
|
mem_addr_26_17 => io_dout(9 downto 0),
|
mem_addr_26_17 => io_dout(9 downto 0),
|
mem_addr_26_17_we => mem_addr_26_17_we,
|
mem_addr_26_17_we => mem_addr_26_17_we,
|
mem_control_i => io_dout(15 downto 10),
|
mem_control_i => io_dout(15 downto 10),
|
mem_control_we => mem_control_we,
|
mem_control_we => mem_control_we,
|
mem_data_i => io_dout,
|
mem_data_i => io_dout,
|
mem_data_i_we => mem_data_i_we,
|
mem_data_i_we => mem_data_i_we,
|
mem_data_o => mem_data_o,
|
mem_data_o => mem_data_o,
|
RamCS => RamCS,
|
ram_cs => ram_cs,
|
MemOE => MemOE,
|
mem_oe => mem_oe,
|
MemWR => MemWR,
|
mem_wr => mem_wr,
|
MemAdv => MemAdv,
|
mem_adv => mem_adv,
|
MemWait => MemWait,
|
mem_wait => mem_wait,
|
FlashCS => FlashCS,
|
flash_cs => flash_cs,
|
FlashRp => FlashRp,
|
flash_rp => flash_rp,
|
MemAdr => MemAdr,
|
mem_addr => mem_addr,
|
MemDB => MemDB);
|
mem_data => mem_data);
|
--- Memory Interface ----------------------------------------------
|
--- Memory Interface ----------------------------------------------
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
end architecture;
|
end architecture;
|
|
|
