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Subversion Repositories fpuvhdl

[/] [fpuvhdl/] [trunk/] [fpuvhdl/] [adder/] [fpadd_normalize_struct.vhd] - Diff between revs 5 and 8

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Rev 5 Rev 8
Line 58... Line 58...
   SIGNAL count      : std_logic_vector(4 DOWNTO 0);
   SIGNAL count      : std_logic_vector(4 DOWNTO 0);
   SIGNAL isDN       : std_logic;
   SIGNAL isDN       : std_logic;
   SIGNAL shift_RL   : std_logic;
   SIGNAL shift_RL   : std_logic;
   SIGNAL word       : std_logic_vector(26 DOWNTO 0);
   SIGNAL word       : std_logic_vector(26 DOWNTO 0);
   SIGNAL zero_int   : std_logic;
   SIGNAL zero_int   : std_logic;
 
   SIGNAL denormal   : std_logic;
 
        SIGNAL lshift_cnt : std_logic_vector(4 DOWNTO 0);
 
 
   -- Component Declarations
   -- Component Declarations
   COMPONENT FPlzc
   COMPONENT FPlzc
   PORT (
   PORT (
      word  : IN     std_logic_vector (26 DOWNTO 0);
      word  : IN     std_logic_vector (26 DOWNTO 0);
Line 85... Line 86...
 
 
   -- HDL Embedded Text Block 2 eb2
   -- HDL Embedded Text Block 2 eb2
   -- eb2 2                    
   -- eb2 2                    
   add_in <= "000" & count;
   add_in <= "000" & count;
 
 
 
        -- limit the count to the exponent value
 
        PROCESS(count,EXP_in)
 
        BEGIN
 
                IF (signed(count) > signed(EXP_in)) THEN
 
                        lshift_cnt <= EXP_in(4 downto 0)-1;
 
                        denormal <= '1';
 
                ELSE
 
                        lshift_cnt <= count;
 
                        denormal <= '0';
 
                END IF;
 
        END PROCESS;
 
 
   -- HDL Embedded Text Block 3 eb3
   -- HDL Embedded Text Block 3 eb3
   -- eb3 3
   -- eb3 3
   PROCESS( isDN, shift_RL, EXP_lshift, EXP_rshift, EXP_in, SIG_lshift, SIG_rshift, SIG_in)
   PROCESS( isDN, shift_RL, EXP_lshift, EXP_rshift, EXP_in, SIG_lshift, SIG_rshift, SIG_in, denormal)
   BEGIN
   BEGIN
   IF (isDN='1') THEN
   IF (isDN='1') THEN
      EXP_out <= X"00";
      EXP_out <= X"00";
      SIG_out <= SIG_in;
      SIG_out <= SIG_in;
   ELSE
   ELSE
Line 104... Line 117...
            EXP_out <= EXP_in;
            EXP_out <= EXP_in;
            SIG_out <= SIG_in;
            SIG_out <= SIG_in;
         END IF;
         END IF;
      ELSE
      ELSE
         -- Shift Left
         -- Shift Left
 
                        IF (denormal='1') THEN
 
                                EXP_out <= (OTHERS => '0');
 
                                SIG_out <= SIG_lshift;
 
                        ELSE
         EXP_out <= EXP_lshift;
         EXP_out <= EXP_lshift;
         SIG_out <= SIG_lshift;
         SIG_out <= SIG_lshift;
      END IF;
      END IF;
   END IF;
   END IF;
 
   END IF;
   END PROCESS;
   END PROCESS;
 
 
   -- HDL Embedded Text Block 4 eb4
   -- HDL Embedded Text Block 4 eb4
   -- eb4 4
   -- eb4 4
   zero <= zero_int AND NOT SIG_in(27);
   zero <= zero_int AND NOT SIG_in(27);
Line 151... Line 169...
      sum := (signed(t0) + '1');
      sum := (signed(t0) + '1');
      EXP_rshift <= conv_std_logic_vector(sum(7 DOWNTO 0),8);
      EXP_rshift <= conv_std_logic_vector(sum(7 DOWNTO 0),8);
   END PROCESS I4combo;
   END PROCESS I4combo;
 
 
   -- ModuleWare code(v1.1) for instance 'I1' of 'lshift'
   -- ModuleWare code(v1.1) for instance 'I1' of 'lshift'
   I1combo : PROCESS (SIG_in, count)
   I1combo : PROCESS (SIG_in, lshift_cnt)
   VARIABLE stemp : std_logic_vector (4 DOWNTO 0);
   VARIABLE stemp : std_logic_vector (4 DOWNTO 0);
   VARIABLE dtemp : std_logic_vector (27 DOWNTO 0);
   VARIABLE dtemp : std_logic_vector (27 DOWNTO 0);
   VARIABLE temp : std_logic_vector (27 DOWNTO 0);
   VARIABLE temp : std_logic_vector (27 DOWNTO 0);
   BEGIN
   BEGIN
      temp := (OTHERS=> 'X');
      temp := (OTHERS=> 'X');
      stemp := count;
      stemp := lshift_cnt;
      temp := SIG_in;
      temp := SIG_in;
      FOR i IN 4 DOWNTO 0 LOOP
      FOR i IN 4 DOWNTO 0 LOOP
         IF (i < 5) THEN
         IF (i < 5) THEN
            IF (stemp(i) = '1' OR stemp(i) = 'H') THEN
            IF (stemp(i) = '1' OR stemp(i) = 'H') THEN
               dtemp := (OTHERS => '0');
               dtemp := (OTHERS => '0');

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