| Line 58... |
Line 58... |
SIGNAL count : std_logic_vector(4 DOWNTO 0);
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SIGNAL count : std_logic_vector(4 DOWNTO 0);
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SIGNAL isDN : std_logic;
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SIGNAL isDN : std_logic;
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SIGNAL shift_RL : std_logic;
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SIGNAL shift_RL : std_logic;
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SIGNAL word : std_logic_vector(26 DOWNTO 0);
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SIGNAL word : std_logic_vector(26 DOWNTO 0);
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SIGNAL zero_int : std_logic;
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SIGNAL zero_int : std_logic;
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SIGNAL denormal : std_logic;
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SIGNAL lshift_cnt : std_logic_vector(4 DOWNTO 0);
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-- Component Declarations
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-- Component Declarations
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COMPONENT FPlzc
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COMPONENT FPlzc
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PORT (
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PORT (
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word : IN std_logic_vector (26 DOWNTO 0);
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word : IN std_logic_vector (26 DOWNTO 0);
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| Line 85... |
Line 86... |
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-- HDL Embedded Text Block 2 eb2
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-- HDL Embedded Text Block 2 eb2
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-- eb2 2
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-- eb2 2
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add_in <= "000" & count;
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add_in <= "000" & count;
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-- limit the count to the exponent value
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PROCESS(count,EXP_in)
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BEGIN
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IF (signed(count) > signed(EXP_in)) THEN
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lshift_cnt <= EXP_in(4 downto 0)-1;
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denormal <= '1';
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ELSE
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lshift_cnt <= count;
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denormal <= '0';
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END IF;
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END PROCESS;
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-- HDL Embedded Text Block 3 eb3
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-- HDL Embedded Text Block 3 eb3
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-- eb3 3
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-- eb3 3
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PROCESS( isDN, shift_RL, EXP_lshift, EXP_rshift, EXP_in, SIG_lshift, SIG_rshift, SIG_in)
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PROCESS( isDN, shift_RL, EXP_lshift, EXP_rshift, EXP_in, SIG_lshift, SIG_rshift, SIG_in, denormal)
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BEGIN
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BEGIN
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IF (isDN='1') THEN
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IF (isDN='1') THEN
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EXP_out <= X"00";
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EXP_out <= X"00";
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SIG_out <= SIG_in;
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SIG_out <= SIG_in;
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ELSE
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ELSE
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| Line 104... |
Line 117... |
EXP_out <= EXP_in;
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EXP_out <= EXP_in;
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SIG_out <= SIG_in;
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SIG_out <= SIG_in;
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END IF;
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END IF;
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ELSE
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ELSE
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-- Shift Left
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-- Shift Left
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IF (denormal='1') THEN
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EXP_out <= (OTHERS => '0');
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SIG_out <= SIG_lshift;
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ELSE
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EXP_out <= EXP_lshift;
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EXP_out <= EXP_lshift;
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SIG_out <= SIG_lshift;
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SIG_out <= SIG_lshift;
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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-- HDL Embedded Text Block 4 eb4
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-- HDL Embedded Text Block 4 eb4
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-- eb4 4
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-- eb4 4
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zero <= zero_int AND NOT SIG_in(27);
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zero <= zero_int AND NOT SIG_in(27);
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| Line 151... |
Line 169... |
sum := (signed(t0) + '1');
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sum := (signed(t0) + '1');
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EXP_rshift <= conv_std_logic_vector(sum(7 DOWNTO 0),8);
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EXP_rshift <= conv_std_logic_vector(sum(7 DOWNTO 0),8);
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END PROCESS I4combo;
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END PROCESS I4combo;
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-- ModuleWare code(v1.1) for instance 'I1' of 'lshift'
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-- ModuleWare code(v1.1) for instance 'I1' of 'lshift'
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I1combo : PROCESS (SIG_in, count)
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I1combo : PROCESS (SIG_in, lshift_cnt)
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VARIABLE stemp : std_logic_vector (4 DOWNTO 0);
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VARIABLE stemp : std_logic_vector (4 DOWNTO 0);
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VARIABLE dtemp : std_logic_vector (27 DOWNTO 0);
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VARIABLE dtemp : std_logic_vector (27 DOWNTO 0);
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VARIABLE temp : std_logic_vector (27 DOWNTO 0);
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VARIABLE temp : std_logic_vector (27 DOWNTO 0);
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BEGIN
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BEGIN
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temp := (OTHERS=> 'X');
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temp := (OTHERS=> 'X');
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stemp := count;
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stemp := lshift_cnt;
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temp := SIG_in;
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temp := SIG_in;
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FOR i IN 4 DOWNTO 0 LOOP
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FOR i IN 4 DOWNTO 0 LOOP
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IF (i < 5) THEN
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IF (i < 5) THEN
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IF (stemp(i) = '1' OR stemp(i) = 'H') THEN
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IF (stemp(i) = '1' OR stemp(i) = 'H') THEN
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dtemp := (OTHERS => '0');
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dtemp := (OTHERS => '0');
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