-- VHDL Entity work.FPadd_normalize.symbol
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-- VHDL Entity work.FPadd_normalize.symbol
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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-- using Mentor Graphics FPGA Advantage tools.
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--
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- 2003-2004. V1.0
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-- 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ENTITY FPadd_normalize IS
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ENTITY FPadd_normalize IS
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PORT(
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PORT(
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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SIG_in : IN std_logic_vector (27 DOWNTO 0);
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SIG_in : IN std_logic_vector (27 DOWNTO 0);
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EXP_out : OUT std_logic_vector (7 DOWNTO 0);
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EXP_out : OUT std_logic_vector (7 DOWNTO 0);
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SIG_out : OUT std_logic_vector (27 DOWNTO 0);
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SIG_out : OUT std_logic_vector (27 DOWNTO 0);
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zero : OUT std_logic
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zero : OUT std_logic
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);
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);
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-- Declarations
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-- Declarations
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END FPadd_normalize ;
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END FPadd_normalize ;
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--
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--
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-- VHDL Architecture work.FPadd_normalize.struct
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-- VHDL Architecture work.FPadd_normalize.struct
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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-- using Mentor Graphics FPGA Advantage tools.
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--
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- Copyright 2003-2004. V1.0
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-- Copyright 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_unsigned.all;
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USE ieee.std_logic_unsigned.all;
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ARCHITECTURE struct OF FPadd_normalize IS
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ARCHITECTURE struct OF FPadd_normalize IS
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-- Architecture declarations
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-- Architecture declarations
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-- Internal signal declarations
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-- Internal signal declarations
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SIGNAL EXP_lshift : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_lshift : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_rshift : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_rshift : std_logic_vector(7 DOWNTO 0);
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SIGNAL SIG_lshift : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_lshift : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_rshift : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_rshift : std_logic_vector(27 DOWNTO 0);
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SIGNAL add_in : std_logic_vector(7 DOWNTO 0);
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SIGNAL add_in : std_logic_vector(7 DOWNTO 0);
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SIGNAL cin : std_logic;
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SIGNAL cin : std_logic;
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SIGNAL count : std_logic_vector(4 DOWNTO 0);
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SIGNAL count : std_logic_vector(4 DOWNTO 0);
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SIGNAL isDN : std_logic;
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SIGNAL isDN : std_logic;
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SIGNAL shift_RL : std_logic;
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SIGNAL shift_RL : std_logic;
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SIGNAL word : std_logic_vector(26 DOWNTO 0);
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SIGNAL word : std_logic_vector(26 DOWNTO 0);
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SIGNAL zero_int : std_logic;
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SIGNAL zero_int : std_logic;
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SIGNAL denormal : std_logic;
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SIGNAL lshift_cnt : std_logic_vector(4 DOWNTO 0);
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-- Component Declarations
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-- Component Declarations
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COMPONENT FPlzc
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COMPONENT FPlzc
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PORT (
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PORT (
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word : IN std_logic_vector (26 DOWNTO 0);
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word : IN std_logic_vector (26 DOWNTO 0);
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zero : OUT std_logic ;
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zero : OUT std_logic ;
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count : OUT std_logic_vector (4 DOWNTO 0)
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count : OUT std_logic_vector (4 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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-- Optional embedded configurations
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-- Optional embedded configurations
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-- pragma synthesis_off
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-- pragma synthesis_off
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FOR ALL : FPlzc USE ENTITY work.FPlzc;
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FOR ALL : FPlzc USE ENTITY work.FPlzc;
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-- pragma synthesis_on
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-- pragma synthesis_on
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BEGIN
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BEGIN
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-- Architecture concurrent statements
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 eb1
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-- HDL Embedded Text Block 1 eb1
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-- eb1 1
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-- eb1 1
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SIG_rshift <= '0' & SIG_in(27 DOWNTO 2) & (SIG_in(1) AND SIG_in(0));
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SIG_rshift <= '0' & SIG_in(27 DOWNTO 2) & (SIG_in(1) AND SIG_in(0));
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-- HDL Embedded Text Block 2 eb2
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-- HDL Embedded Text Block 2 eb2
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-- eb2 2
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-- eb2 2
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add_in <= "000" & count;
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add_in <= "000" & count;
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-- limit the count to the exponent value
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PROCESS(count,EXP_in)
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BEGIN
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IF (signed(count) > signed(EXP_in)) THEN
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lshift_cnt <= EXP_in(4 downto 0)-1;
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denormal <= '1';
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ELSE
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lshift_cnt <= count;
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denormal <= '0';
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END IF;
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END PROCESS;
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-- HDL Embedded Text Block 3 eb3
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-- HDL Embedded Text Block 3 eb3
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-- eb3 3
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-- eb3 3
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PROCESS( isDN, shift_RL, EXP_lshift, EXP_rshift, EXP_in, SIG_lshift, SIG_rshift, SIG_in)
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PROCESS( isDN, shift_RL, EXP_lshift, EXP_rshift, EXP_in, SIG_lshift, SIG_rshift, SIG_in, denormal)
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BEGIN
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BEGIN
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IF (isDN='1') THEN
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IF (isDN='1') THEN
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EXP_out <= X"00";
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EXP_out <= X"00";
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SIG_out <= SIG_in;
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SIG_out <= SIG_in;
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ELSE
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ELSE
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IF (shift_RL='1') THEN
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IF (shift_RL='1') THEN
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-- Shift Right
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-- Shift Right
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IF (SIG_in(27)='1') THEN
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IF (SIG_in(27)='1') THEN
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EXP_out <= EXP_rshift;
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EXP_out <= EXP_rshift;
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SIG_out <= SIG_rshift;
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SIG_out <= SIG_rshift;
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ELSE
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ELSE
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EXP_out <= EXP_in;
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EXP_out <= EXP_in;
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SIG_out <= SIG_in;
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SIG_out <= SIG_in;
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END IF;
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END IF;
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ELSE
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ELSE
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-- Shift Left
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-- Shift Left
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IF (denormal='1') THEN
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EXP_out <= (OTHERS => '0');
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SIG_out <= SIG_lshift;
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ELSE
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EXP_out <= EXP_lshift;
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EXP_out <= EXP_lshift;
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SIG_out <= SIG_lshift;
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SIG_out <= SIG_lshift;
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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-- HDL Embedded Text Block 4 eb4
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-- HDL Embedded Text Block 4 eb4
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-- eb4 4
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-- eb4 4
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zero <= zero_int AND NOT SIG_in(27);
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zero <= zero_int AND NOT SIG_in(27);
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-- HDL Embedded Text Block 5 eb5
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-- HDL Embedded Text Block 5 eb5
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-- eb5 5
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-- eb5 5
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word <= SIG_in(26 DOWNTO 0);
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word <= SIG_in(26 DOWNTO 0);
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-- HDL Embedded Text Block 6 eb6
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-- HDL Embedded Text Block 6 eb6
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-- eb6 6
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-- eb6 6
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PROCESS(SIG_in,EXP_in)
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PROCESS(SIG_in,EXP_in)
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BEGIN
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BEGIN
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IF (SIG_in(27)='0' AND SIG_in(26)='0' AND (EXP_in=X"01")) THEN
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IF (SIG_in(27)='0' AND SIG_in(26)='0' AND (EXP_in=X"01")) THEN
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isDN <= '1';
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isDN <= '1';
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shift_RL <= '0';
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shift_RL <= '0';
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ELSIF (SIG_in(27)='0' AND SIG_in(26)='0' AND (EXP_in/=X"00")) THEN
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ELSIF (SIG_in(27)='0' AND SIG_in(26)='0' AND (EXP_in/=X"00")) THEN
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isDN <= '0';
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isDN <= '0';
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shift_RL <= '0';
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shift_RL <= '0';
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ELSE
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ELSE
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isDN <= '0';
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isDN <= '0';
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shift_RL <= '1';
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shift_RL <= '1';
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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-- ModuleWare code(v1.1) for instance 'I3' of 'gnd'
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-- ModuleWare code(v1.1) for instance 'I3' of 'gnd'
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cin <= '0';
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cin <= '0';
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-- ModuleWare code(v1.1) for instance 'I4' of 'inc'
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-- ModuleWare code(v1.1) for instance 'I4' of 'inc'
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I4combo: PROCESS (EXP_in)
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I4combo: PROCESS (EXP_in)
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VARIABLE t0 : std_logic_vector(8 DOWNTO 0);
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VARIABLE t0 : std_logic_vector(8 DOWNTO 0);
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VARIABLE sum : signed(8 DOWNTO 0);
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VARIABLE sum : signed(8 DOWNTO 0);
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VARIABLE din_l : std_logic_vector(7 DOWNTO 0);
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VARIABLE din_l : std_logic_vector(7 DOWNTO 0);
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BEGIN
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BEGIN
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din_l := EXP_in;
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din_l := EXP_in;
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t0 := din_l(7) & din_l;
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t0 := din_l(7) & din_l;
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sum := (signed(t0) + '1');
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sum := (signed(t0) + '1');
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EXP_rshift <= conv_std_logic_vector(sum(7 DOWNTO 0),8);
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EXP_rshift <= conv_std_logic_vector(sum(7 DOWNTO 0),8);
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END PROCESS I4combo;
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END PROCESS I4combo;
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-- ModuleWare code(v1.1) for instance 'I1' of 'lshift'
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-- ModuleWare code(v1.1) for instance 'I1' of 'lshift'
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I1combo : PROCESS (SIG_in, count)
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I1combo : PROCESS (SIG_in, lshift_cnt)
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VARIABLE stemp : std_logic_vector (4 DOWNTO 0);
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VARIABLE stemp : std_logic_vector (4 DOWNTO 0);
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VARIABLE dtemp : std_logic_vector (27 DOWNTO 0);
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VARIABLE dtemp : std_logic_vector (27 DOWNTO 0);
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VARIABLE temp : std_logic_vector (27 DOWNTO 0);
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VARIABLE temp : std_logic_vector (27 DOWNTO 0);
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BEGIN
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BEGIN
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temp := (OTHERS=> 'X');
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temp := (OTHERS=> 'X');
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stemp := count;
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stemp := lshift_cnt;
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temp := SIG_in;
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temp := SIG_in;
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FOR i IN 4 DOWNTO 0 LOOP
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FOR i IN 4 DOWNTO 0 LOOP
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IF (i < 5) THEN
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IF (i < 5) THEN
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IF (stemp(i) = '1' OR stemp(i) = 'H') THEN
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IF (stemp(i) = '1' OR stemp(i) = 'H') THEN
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dtemp := (OTHERS => '0');
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dtemp := (OTHERS => '0');
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dtemp(27 DOWNTO 2**i) := temp(27 - 2**i DOWNTO 0);
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dtemp(27 DOWNTO 2**i) := temp(27 - 2**i DOWNTO 0);
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ELSIF (stemp(i) = '0' OR stemp(i) = 'L') THEN
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ELSIF (stemp(i) = '0' OR stemp(i) = 'L') THEN
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dtemp := temp;
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dtemp := temp;
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ELSE
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ELSE
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dtemp := (OTHERS => 'X');
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dtemp := (OTHERS => 'X');
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END IF;
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END IF;
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ELSE
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ELSE
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IF (stemp(i) = '1' OR stemp(i) = 'H') THEN
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IF (stemp(i) = '1' OR stemp(i) = 'H') THEN
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dtemp := (OTHERS => '0');
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dtemp := (OTHERS => '0');
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ELSIF (stemp(i) = '0' OR stemp(i) = 'L') THEN
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ELSIF (stemp(i) = '0' OR stemp(i) = 'L') THEN
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dtemp := temp;
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dtemp := temp;
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ELSE
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ELSE
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dtemp := (OTHERS => 'X');
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dtemp := (OTHERS => 'X');
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END IF;
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END IF;
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END IF;
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END IF;
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temp := dtemp;
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temp := dtemp;
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END LOOP;
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END LOOP;
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SIG_lshift <= dtemp;
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SIG_lshift <= dtemp;
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END PROCESS I1combo;
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END PROCESS I1combo;
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-- ModuleWare code(v1.1) for instance 'I2' of 'sub'
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-- ModuleWare code(v1.1) for instance 'I2' of 'sub'
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I2combo: PROCESS (EXP_in, add_in, cin)
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I2combo: PROCESS (EXP_in, add_in, cin)
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VARIABLE mw_I2t0 : std_logic_vector(8 DOWNTO 0);
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VARIABLE mw_I2t0 : std_logic_vector(8 DOWNTO 0);
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VARIABLE mw_I2t1 : std_logic_vector(8 DOWNTO 0);
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VARIABLE mw_I2t1 : std_logic_vector(8 DOWNTO 0);
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VARIABLE diff : signed(8 DOWNTO 0);
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VARIABLE diff : signed(8 DOWNTO 0);
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VARIABLE borrow : std_logic;
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VARIABLE borrow : std_logic;
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BEGIN
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BEGIN
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mw_I2t0 := EXP_in(7) & EXP_in;
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mw_I2t0 := EXP_in(7) & EXP_in;
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mw_I2t1 := add_in(7) & add_in;
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mw_I2t1 := add_in(7) & add_in;
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borrow := cin;
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borrow := cin;
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diff := signed(mw_I2t0) - signed(mw_I2t1) - borrow;
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diff := signed(mw_I2t0) - signed(mw_I2t1) - borrow;
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EXP_lshift <= conv_std_logic_vector(diff(7 DOWNTO 0),8);
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EXP_lshift <= conv_std_logic_vector(diff(7 DOWNTO 0),8);
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END PROCESS I2combo;
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END PROCESS I2combo;
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-- Instance port mappings.
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-- Instance port mappings.
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I0 : FPlzc
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I0 : FPlzc
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PORT MAP (
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PORT MAP (
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word => word,
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word => word,
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zero => zero_int,
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zero => zero_int,
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count => count
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count => count
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);
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);
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END struct;
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END struct;
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