`include "positConfig.sv"
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`include "positConfig.sv"
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// positDecompose.sv
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// positDecompose.sv
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see .
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// along with this program. If not, see .
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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`include "positConfig.sv"
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`include "positConfig.sv"
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// Decompose a posit number.
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// Decompose a posit number.
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module positDecompose(i, sgn, rgs, rgm, exp, sig, zer, inf);
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module positDecompose(i, sgn, rgs, rgm, exp, sig, zer, inf);
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`include "positSize.sv"
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`include "positSize.sv"
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localparam rs = $clog2(PSTWID-1);
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localparam rs = $clog2(PSTWID-1);
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input [PSTWID-1:0] i;
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input [PSTWID-1:0] i;
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output sgn; // sign of number
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output sgn; // sign of number
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output rgs; // sign of regime
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output rgs; // sign of regime
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output [rs:0] rgm; // regime (absolute value)
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output [rs:0] rgm; // regime (absolute value)
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output [es-1:0] exp; // exponent
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output [es-1:0] exp; // exponent
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output [PSTWID-1-es:0] sig; // significand
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output [PSTWID-1-es:0] sig; // significand
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output zer; // number is zero
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output zer; // number is zero
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output inf; // number is infinite
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output inf; // number is infinite
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wire [rs:0] lzcnt;
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wire [rs-1:0] lzcnt;
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wire [rs:0] locnt;
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wire [rs-1:0] locnt;
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assign sgn = i[PSTWID-1];
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assign sgn = i[PSTWID-1];
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assign inf = ~|i[PSTWID-2:0] & i[PSTWID-1];
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assign inf = ~|i[PSTWID-2:0] & i[PSTWID-1];
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assign zer = ~|i;
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assign zer = ~|i;
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wire [PSTWID-1:0] ii = sgn ? -i : i;
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wire [PSTWID-1:0] ii = sgn ? -i : i;
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assign rgs = ii[PSTWID-2];
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assign rgs = ii[PSTWID-2];
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positCntlz #(PSTWID) u1 (.i(ii[PSTWID-2:0]), .o(lzcnt));
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positCntlz #(PSTWID) u1 (.i(ii[PSTWID-2:0]), .o(lzcnt));
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positCntlo #(PSTWID) u2 (.i(ii[PSTWID-2:0]), .o(locnt));
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positCntlo #(PSTWID) u2 (.i(ii[PSTWID-2:0]), .o(locnt));
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assign rgm = rgs ? locnt - 1 : lzcnt;
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assign rgm = rgs ? locnt - 1 : lzcnt;
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wire [rs:0] shamt = rgs ? locnt + 2'd1 : lzcnt + 2'd1;
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wire [rs:0] shamt = rgs ? locnt + 2'd1 : lzcnt + 2'd1;
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wire [PSTWID-1:0] tmp = ii << shamt;
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wire [PSTWID-1:0] tmp = ii << shamt;
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assign exp = |es ? tmp[PSTWID-2:PSTWID-1-es] : 0;
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assign exp = |es ? tmp[PSTWID-2:PSTWID-1-es] : 0;
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assign sig = {~zer,tmp[PSTWID-2-es:0]};
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assign sig = {~zer,tmp[PSTWID-2-es:0]};
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endmodule
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endmodule
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// Decompose posit number and register outputs.
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// Decompose posit number and register outputs.
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module positDecomposeReg(clk, ce, i, sgn, rgs, rgm, exp, sig, zer, inf);
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module positDecomposeReg(clk, ce, i, sgn, rgs, rgm, exp, sig, zer, inf);
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`include "positSize.sv"
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`include "positSize.sv"
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input clk;
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input clk;
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input ce;
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input ce;
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input [PSTWID-1:0] i;
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input [PSTWID-1:0] i;
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output reg sgn;
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output reg sgn;
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output reg rgs;
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output reg rgs;
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output reg [$clog2(PSTWID)-1:0] rgm;
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output reg [$clog2(PSTWID)-1:0] rgm;
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output reg [es-1:0] exp;
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output reg [es-1:0] exp;
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output reg [PSTWID-es-1:0] sig;
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output reg [PSTWID-es-1:0] sig;
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output reg zer;
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output reg zer;
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output reg inf;
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output reg inf;
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wire isgn;
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wire isgn;
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wire irgs;
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wire irgs;
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wire [$clog2(PSTWID)-1:0] irgm;
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wire [$clog2(PSTWID)-1:0] irgm;
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wire [es-1:0] iexp;
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wire [es-1:0] iexp;
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wire [PSTWID-es-1:0] isig;
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wire [PSTWID-es-1:0] isig;
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wire izer;
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wire izer;
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wire iinf;
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wire iinf;
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positDecompose #(PSTWID) u1 (i, isgn, irgs, irgm, iexp, isig, iinf);
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positDecompose #(PSTWID) u1 (i, isgn, irgs, irgm, iexp, isig, iinf);
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always @(posedge clk)
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always @(posedge clk)
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if (ce) begin
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if (ce) begin
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sgn = isgn;
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sgn = isgn;
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rgs = irgs;
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rgs = irgs;
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rgm = irgm;
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rgm = irgm;
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exp = iexp;
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exp = iexp;
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sig = isig;
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sig = isig;
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inf = iinf;
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inf = iinf;
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end
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end
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endmodule
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endmodule
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