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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPDecompose.sv] - Diff between revs 50 and 51

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Rev 50 Rev 51
Line 44... Line 44...
output xz;
output xz;
output vz;
output vz;
output inf;
output inf;
output nan;
output nan;
 
 
assign nan = i[115];
assign nan = i[127];
assign sgn = i[114];
assign sgn = i[126];
assign inf = i[113];
assign inf = i[125];
assign sx = i[112];
assign sx = i[124];
assign exp = i[111:96];
assign exp = i[123:108];
assign sig = i[95:0];
assign sig = i[107:0];
assign xz = ~|exp;
assign xz = ~|exp;
assign vz = ~|{exp,sig};
assign vz = ~|{exp,sig};
 
 
endmodule
endmodule
 
 
Line 63... Line 63...
input ce;
input ce;
input [127:0] i;
input [127:0] i;
output reg sgn;
output reg sgn;
output reg sx;
output reg sx;
output reg [15:0] exp;
output reg [15:0] exp;
output reg [95:0] sig;
output reg [107:0] sig;
output reg xz;
output reg xz;
output reg vz;
output reg vz;
output reg inf;
output reg inf;
output reg nan;
output reg nan;
 
 
always @(posedge clk)
always @(posedge clk)
        if (ce) begin
        if (ce) begin
                nan <= i[115];
                nan <= i[127];
                sgn <= i[114];
                sgn <= i[126];
                inf <= i[113];
                inf <= i[125];
                sx <= i[112];
                sx <= i[124];
                exp <= i[111:96];
                exp <= i[123:108];
                sig <= i[95:0];
                sig <= i[107:0];
                xz <= ~|exp;
                xz <= ~|exp;
                vz <= ~|{exp,sig};
                vz <= ~|{exp,sig};
        end
        end
 
 
endmodule
endmodule

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