| Line 132... |
Line 132... |
// Clock #2 to N
|
// Clock #2 to N
|
// - calculate fraction
|
// - calculate fraction
|
// -----------------------------------------------------------
|
// -----------------------------------------------------------
|
wire done3a,done3;
|
wire done3a,done3;
|
// Perform divide
|
// Perform divide
|
dfdiv #(N+2) u2 (.clk(clk), .ld(ld1), .a({siga,8'b0}), .b({sigb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
|
dfdiv2 #(N+2) u2 (.clk(clk), .ld(ld1), .a({siga,8'b0}), .b({sigb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
|
wire [7:0] lzcnt_bin = lzcnt[3:0] + (lzcnt[7:4] * 10);
|
//wire [7:0] lzcnt_bin = lzcnt[3:0] + (lzcnt[7:4] * 10);
|
wire [(N+2)*4*2-1:0] divo1 = divo[(N+2)*4*2-1:0] << ({lzcnt_bin,2'b0}+N*4);//WAS FPWID=128?+44
|
wire [(N+2)*4*2-1:0] divo1 = divo[(N+2)*4*2-1:0] << ({lzcnt-1,2'b0});//WAS FPWID=128?+44
|
ft_delay #(.WID(1), .DEP(3)) u3 (.clk(clk), .ce(ce), .i(done1), .o(done3a));
|
ft_delay #(.WID(1), .DEP(3)) u3 (.clk(clk), .ce(ce), .i(done1), .o(done3a));
|
assign done3 = done1&done3a;
|
assign done3 = done1&done3a;
|
|
|
// -----------------------------------------------------------
|
// -----------------------------------------------------------
|
// Clock #N+1
|
// Clock #N+1
|
| Line 152... |
Line 152... |
// - also factor in the different decimal position for division
|
// - also factor in the different decimal position for division
|
reg [13:0] ex1; // sum of exponents
|
reg [13:0] ex1; // sum of exponents
|
reg qNaNOut;
|
reg qNaNOut;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) ex1 <= au.exp - bu.exp + bias - lzcnt_bin;
|
if (ce) ex1 <= au.exp - bu.exp + bias - (({lzcnt,2'b00} > N+2) ? lzcnt-(N+2) : 0);
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (ce) qNaNOut <= (az&bz)|(aInf&bInf);
|
if (ce) qNaNOut <= (az&bz)|(aInf&bInf);
|
|
|
wire over = 1'b0;
|
wire over = 1'b0;
|
