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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPSqrt96.sv] - Diff between revs 75 and 78

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Rev 75 Rev 78
Line 38... Line 38... 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
//
 
//
 
// ============================================================================
 
// ============================================================================
 
 
 
 
 
import DFPPkg::*;
 
import DFPPkg::*;
 
import fp::*;
 
 
 
 
 
 
 
module DFPSqrt96(rst, clk, ce, ld, a, o, done, sqrinf, sqrneg);
 
module DFPSqrt96(rst, clk, ce, ld, a, o, done, sqrinf, sqrneg);
 
parameter N=25;
 
parameter N=25;
 
localparam pShiftAmt =
 
 
 
        FPWID==80 ? 48 :
 
 
 
        FPWID==64 ? 36 :
 
 
 
        FPWID==32 ? 7 : (FMSB+1-16);
 
 
 
input rst;
 
input rst;
 
input clk;
 
input clk;
 
input ce;
 
input ce;
 
input ld;
 
input ld;
 
input DFP96 a;
 
input DFP96 a;
Line 61... Line 56... 
// registered outputs
 
// registered outputs
 
reg sign_exe;
 
reg sign_exe;
 
reg inf;
 
reg inf;
 
reg     overflow;
 
reg     overflow;
 
reg     underflow;
 
reg     underflow;
 
 
 
wire sign = 1'b0;
 
 
 
 
 
wire so;
 
wire so;
 
wire [13:0] xo;
 
wire [13:0] xo;
 
wire [(N+1)*4*2-1:0] mo;
 
wire [(N+1)*4*2-1:0] mo;
 
 
 
 

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