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https://opencores.org/ocsvn/ft816float/ft816float/trunk
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| Rev 82 |
Rev 84 |
| Line 64... |
Line 64... |
reg [5:0] digcnt;
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reg [5:0] digcnt;
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reg [FPWID*2-1:0] qi;
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reg [FPWID*2-1:0] qi;
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reg [FPWID+3:0] ri;
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reg [FPWID+3:0] ri;
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reg [FPWID-1:0] bi;
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reg [FPWID-1:0] bi;
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wire sgn;
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wire sgn;
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wire [FPWID-1:0] dif;
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wire [FPWID+3:0] dif;
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reg gotnz; // got a non-zero digit
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reg gotnz; // got a non-zero digit
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generate begin : gSub
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generate begin : gSub
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BCDSubtract #(.N(N)) ubcds1
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BCDSubtract #(.N(N+1)) ubcds1
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(
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(
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.clk(clk),
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.clk(clk),
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.a(ri),
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.a(ri),
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.b(bi),
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.b({4'b0,bi}),
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.o(dif),
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.o(dif),
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.sgn(sgn)
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.sgn(sgn)
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);
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);
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end
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end
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endgenerate
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endgenerate
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| Line 116... |
Line 116... |
begin
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begin
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digcnt <= digcnt - 1'd1;
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digcnt <= digcnt - 1'd1;
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if (digcnt=='d0) begin
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if (digcnt=='d0) begin
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clkcnt <= clkcnt + 1'd1;
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clkcnt <= clkcnt + 1'd1;
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digcnt <= 6'd10;
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digcnt <= 6'd10;
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if (sgn) begin
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if (bi > ri) begin
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ri <= {ri,qi[FPWID*2-1:FPWID*2-4]};
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ri <= {ri,qi[FPWID*2-1:FPWID*2-4]};
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qi <= {qi[FPWID*2-5:0],cnt};
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qi <= {qi[FPWID*2-5:0],cnt};
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cnt <= 4'd0;
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cnt <= 4'd0;
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dcnt <= dcnt - 1'd1;
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dcnt <= dcnt - 1'd1;
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if (dcnt=='d0)
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if (dcnt=='d0)
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st <= DONE;
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st <= DONE;
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end
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end
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else begin
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else begin
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if (clkcnt > 600 && 1'b0) begin
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if (clkcnt > 600 && 0) begin
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ri <= {ri,qi[FPWID*2-1:FPWID*2-4]};
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ri <= {ri,qi[FPWID*2-1:FPWID*2-4]};
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qi <= {qi[FPWID*2-5:0],cntm1};
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qi <= {qi[FPWID*2-5:0],cntm1};
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cnt <= 4'd0;
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cnt <= 4'd0;
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dcnt <= dcnt - 1'd1;
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dcnt <= dcnt - 1'd1;
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if (dcnt==6'd0)
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if (dcnt==6'd0)
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