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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpDiv.v] - Diff between revs 32 and 34

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// ============================================================================
// ============================================================================
//        __
//        __
//   \\__/ o\    (C) 2006-2019  Robert Finch, Waterloo
//   \\__/ o\    (C) 2006-2020  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//       ||
//
//
//      fpDiv.v
//      fpDiv.v
//    - floating point divider
//    - floating point divider
//    - parameterized width
//    - parameterized FPWIDth
//    - IEEE 754 representation
//    - IEEE 754 representation
//
//
//
//
// This source file is free software: you can redistribute it and/or modify 
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// it under the terms of the GNU Lesser General Public License as published 
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//+-inf * 0     = QNaN
//+-inf * 0     = QNaN
//+-0 / +-0      = QNaN
//+-0 / +-0      = QNaN
// ============================================================================
// ============================================================================
 
 
`include "fpConfig.sv"
`include "fpConfig.sv"
`include "fp_defines.v"
`include "fpDefines.v"
//`define GOLDSCHMIDT   1'b1
//`define GOLDSCHMIDT   1'b1
 
 
module fpDiv(rst, clk, clk4x, ce, ld, op, a, b, o, done, sign_exe, overflow, underflow);
module fpDiv(rst, clk, clk4x, ce, ld, op, a, b, o, done, sign_exe, overflow, underflow);
 
 
parameter FPWID = 64;
parameter FPWID = 64;
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localparam FADD = FPWID==128 ? 9 :
localparam FADD = FPWID==128 ? 9 :
                                  FPWID==96 ? 9 :
                                  FPWID==96 ? 9 :
                                  FPWID==84 ? 9 :
                                  FPWID==84 ? 9 :
                                  FPWID==80 ? 9 :
                                  FPWID==80 ? 9 :
                                  FPWID==64 ? 13 :
                                  FPWID==64 ? 13 :
                                  FPWID==52 ? 9 :
                                  FPWID==52 ? 13 :
                                  FPWID==48 ? 10 :
                                  FPWID==48 ? 10 :
                                  FPWID==44 ? 9 :
                                  FPWID==44 ? 9 :
                                  FPWID==42 ? 11 :
                                  FPWID==42 ? 11 :
                                  FPWID==40 ? 8 :
                                  FPWID==40 ? 8 :
                                  FPWID==32 ? 10 :
                                  FPWID==32 ? 10 :
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// Perform divide
// Perform divide
// Divider width must be a multiple of four
// Divider width must be a multiple of four
`ifndef GOLDSCHMIDT
`ifndef GOLDSCHMIDT
fpdivr16 #(FMSB+FADD) u2 (.clk(clk), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
fpdivr16 #(FMSB+FADD) u2 (.clk(clk), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
//fpdivr2 #(FMSB+FADD) u2 (.clk4x(clk4x), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
//fpdivr2 #(FMSB+FADD) u2 (.clk4x(clk4x), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
wire [(FMSB+FADD)*2-1:0] divo1 = divo[(FMSB+FADD)*2-1:0] << (lzcnt-2);
reg [(FMSB+FADD)*2-1:0] divo1;
 
always @(posedge clk)
 
  if (ce) divo1 = divo[(FMSB+FADD)*2-1:0] << (lzcnt-2);
`else
`else
DivGoldschmidt #(.WID(FMSB+6),.WHOLE(1),.POINTS(FMSB+5))
DivGoldschmidt #(.FPWID(FMSB+6),.WHOLE(1),.POINTS(FMSB+5))
        u2 (.rst(rst), .clk(clk), .ld(ld), .a({fracta,4'b0}), .b({fractb,4'b0}), .q(divo), .done(done1), .lzcnt(lzcnt));
        u2 (.rst(rst), .clk(clk), .ld(ld), .a({fracta,4'b0}), .b({fractb,4'b0}), .q(divo), .done(done1), .lzcnt(lzcnt));
wire [(FMSB+6)*2+1:0] divo1 =
reg [(FMSB+6)*2+1:0] divo1;
 
always @(posedge clk)
 
  if (ce) divo1 =
        lzcnt > 8'd5 ? divo << (lzcnt-8'd6) :
        lzcnt > 8'd5 ? divo << (lzcnt-8'd6) :
        divo >> (8'd6-lzcnt);
        divo >> (8'd6-lzcnt);
        ;
        ;
`endif
`endif
delay1 #(1) u3 (.clk(clk), .ce(ce), .i(done1), .o(done));
delay1 #(1) u3 (.clk(clk), .ce(ce), .i(done1), .o(done2));
 
delay2 #(1) u4 (.clk(clk), .ce(ce), .i(done1), .o(done));
 
 
 
 
// determine when a NaN is output
// determine when a NaN is output
wire qNaNOut = (az&bz)|(aInf&bInf);
wire qNaNOut = (az&bz)|(aInf&bInf);
 
 
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        sign_exe <= 1'd0;
        sign_exe <= 1'd0;
        overflow <= 1'd0;
        overflow <= 1'd0;
        underflow <= 1'd0;
        underflow <= 1'd0;
end
end
else if (ce) begin
else if (ce) begin
                if (done1) begin
                if (done2) begin
                        casez({qNaNOut|aNan|bNan,bInf,bz,over,under})
                        casez({qNaNOut|aNan|bNan,bInf,bz,over,under})
                        5'b1????:               xo <= infXp;    // NaN exponent value
                        5'b1????:               xo <= infXp;    // NaN exponent value
                        5'b01???:               xo <= 1'd0;             // divide by inf
                        5'b01???:               xo <= 1'd0;             // divide by inf
                        5'b001??:               xo <= infXp;    // divide by zero
                        5'b001??:               xo <= infXp;    // divide by zero
                        5'b0001?:               xo <= infXp;    // overflow
                        5'b0001?:               xo <= infXp;    // overflow
                        5'b00001:               xo <= 1'd0;             // underflow
                        5'b00001:               xo <= 1'd0;             // underflow
                        default:                xo <= ex1;      // normal or underflow: passthru neg. exp. for normalization
                        default:                xo <= ex1;      // normal or underflow: passthru neg. exp. for normalization
                        endcase
                        endcase
 
 
                        casez({aNan,bNan,qNaNOut,bInf,bz,over,aInf&bInf,az&bz})
                        casez({aNan,bNan,qNaNOut,bInf,bz,over,aInf&bInf,az&bz})
                        8'b1???????:    mo <= {1'b1,a[FMSB:0],{FMSB+1{1'b0}}};
                        8'b1???????:  mo <= {1'b1,1'b1,a[FMSB-1:0],{FMSB+1{1'b0}}};
                        8'b01??????:    mo <= {1'b1,b[FMSB:0],{FMSB+1{1'b0}}};
                        8'b01??????:  mo <= {1'b1,1'b1,b[FMSB-1:0],{FMSB+1{1'b0}}};
                        8'b001?????:    mo <= {1'b1,qNaN[FMSB:0]|{aInf,1'b0}|{az,bz},{FMSB+1{1'b0}}};
                        8'b001?????:    mo <= {1'b1,qNaN[FMSB:0]|{aInf,1'b0}|{az,bz},{FMSB+1{1'b0}}};
                        8'b0001????:    mo <= 1'd0;     // div by inf
                        8'b0001????:    mo <= 1'd0;     // div by inf
                        8'b00001???:    mo <= 1'd0;     // div by zero
                        8'b00001???:    mo <= 1'd0;     // div by zero
                        8'b000001??:    mo <= 1'd0;     // Inf exponent
                        8'b000001??:    mo <= 1'd0;     // Inf exponent
                        8'b0000001?:    mo <= {1'b1,qNaN|`QINFDIV,{FMSB+1{1'b0}}};      // infinity / infinity
                        8'b0000001?:    mo <= {1'b1,qNaN|`QINFDIV,{FMSB+1{1'b0}}};      // infinity / infinity
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fpRound     #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
fpRound     #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
delay2      #(1)   u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
delay2      #(1)   u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
delay2      #(1)   u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
delay2      #(1)   u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
delay2      #(1)   u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
delay2      #(1)   u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
delay2      #(1)   u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
delay2      #(1)   u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
vtdl                    #(1)   u8(.clk(clk), .ce(ce), .a(4'd13), .d(done1), .q(done));
delay2            #(1)   u8(.clk(clk), .ce(ce), .i(done1), .o(done));
endmodule
endmodule
 
 
 
 
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