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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [mult128x128.sv] - Diff between revs 49 and 72

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Rev 49 Rev 72
Line 35... Line 35...
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// ============================================================================
// ============================================================================
 
 
 
//`define KARATSUBA     1
 
 
 
`ifdef KARATSUBA
 
 
module mult128x128(clk, ce, a, b, o);
module mult128x128(clk, ce, a, b, o);
input clk;
input clk;
input ce;
input ce;
input [127:0] a;
input [127:0] a;
input [127:0] b;
input [127:0] b;
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always @(posedge clk)
always @(posedge clk)
        if (ce) b2 <= b1[64] ? -b1 : b1;
        if (ce) b2 <= b1[64] ? -b1 : b1;
always @(posedge clk)
always @(posedge clk)
  if (ce) sgn2 <= a1[64]^b1[64];
  if (ce) sgn2 <= a1[64]^b1[64];
 
 
delay #(.WID(1), .DEP(12)) udl1 (.clk(clk), .ce(ce), .i(sgn2), .o(sgn9));
ft_delay #(.WID(1), .DEP(12)) udl1 (.clk(clk), .ce(ce), .i(sgn2), .o(sgn9));
always @(posedge clk)
always @(posedge clk)
  if (ce) sgn10 <= sgn9;
  if (ce) sgn10 <= sgn9;
 
 
// 11 cycle latency
// 11 cycle latency
mult64x64 u1 (
mult64x64 u1 (
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  if (ce) z0d <= z0c;
  if (ce) z0d <= z0c;
always @(posedge clk)
always @(posedge clk)
        if (ce) o <= {z2d,z0d} + {z1,64'd0};
        if (ce) o <= {z2d,z0d} + {z1,64'd0};
 
 
endmodule
endmodule
 
 
 
`else
 
 
 
// This version of the multiply has a parameterized pipeline depth and allows
 
// the tools to perform the multiply. Relies on the ability of tools to retime.
 
 
 
module mult128x128(clk, ce, a, b, o);
 
parameter DEP = 18;
 
input clk;
 
input ce;
 
input [127:0] a;
 
input [127:0] b;
 
output reg [255:0] o;
 
 
 
reg [255:0] prod [0:DEP-1];
 
reg [255:0] prd;
 
integer n;
 
 
 
always_ff @(posedge clk)
 
        if (ce) prd <= a * b;
 
always_ff @(posedge clk)
 
        if (ce) prod[0] <= prd;
 
 
 
always_ff @(posedge clk)
 
        for (n = 0; n < DEP - 1; n = n + 1)
 
                if (ce) prod[n+1] <= prod[n];
 
 
 
always_ff @(posedge clk)
 
        if(ce) o <= prod[DEP-1];
 
 
 
endmodule
 
 
 
`endif

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