| Line 38... |
Line 38... |
You should have received a copy of the GNU Lesser General
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml.
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from http://www.opencores.org/lgpl.shtml.
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*/
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*/
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library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
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library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
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--use work.types.all;
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/* Enable for synthesis; comment out for simulation.
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For this design, we just need boolean_vector. This is already included in Questa/ModelSim,
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but Quartus doesn't yet support this.
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*/
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use work.types.all;
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entity lfsr is generic(
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entity lfsr is generic(
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/*
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/*
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* Tap vector: a TRUE means that position is tapped, otherwise that position is untapped.
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* Tap vector: a TRUE means that position is tapped, otherwise that position is untapped.
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*/
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*/
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| Line 73... |
Line 77... |
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/* Receives a vector of taps; generates LFSR structure with correct XOR positionings. */
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/* Receives a vector of taps; generates LFSR structure with correct XOR positionings. */
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tapGenr: for i in 0 to taps'high-1 generate
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tapGenr: for i in 0 to taps'high-1 generate
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i_d(i+1)<=x(i) when taps(i) else i_q(i);
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i_d(i+1)<=x(i) when taps(i) else i_q(i);
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x(i)<=i_q(i) xor i_q(taps'high); -- when nReset else '0';
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x(i)<=i_q(i) xor i_q(taps'high);
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end generate;
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end generate;
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process(nReset,load,seed,clk) is begin
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process(nReset,load,seed,clk) is begin
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--if nReset='0' or load then i_q<=seed;
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if nReset='0' then i_q<=(others=>'0');
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if nReset='0' then i_q<=(others=>'0');
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elsif load then i_q<=seed;
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elsif load then i_q<=seed;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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i_q<=i_d;
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i_q<=i_d;
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end if;
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end if;
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