/*
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/*
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This file is part of the Galois Linear Feedback Shift Register
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This file is part of the Galois Linear Feedback Shift Register
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(galois_lfsr) project:
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(galois_lfsr) project:
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http://www.opencores.org/project,galois_lfsr
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http://www.opencores.org/project,galois_lfsr
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Description
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Description
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Synthesisable use case for Galois LFSR.
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Synthesisable use case for Galois LFSR.
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This example is a CRC generator that uses a Galois LFSR.
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This example is a CRC generator that uses a Galois LFSR.
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Example applications include:
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Example applications include:
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* serial or parallel PRBS generation.
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* serial or parallel PRBS generation.
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* CRC computation.
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* CRC computation.
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* digital scramblers/descramblers.
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* digital scramblers/descramblers.
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ToDo:
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ToDo:
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Author(s):
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Author(s):
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- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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This source file is free software; you can redistribute it
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and/or modify it under the terms of the GNU Lesser General
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and/or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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either version 2.1 of the License, or (at your option) any
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later version.
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later version.
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This source is distributed in the hope that it will be
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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details.
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You should have received a copy of the GNU Lesser General
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml.
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from http://www.opencores.org/lgpl.shtml.
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*/
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*/
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library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
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library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
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--use work.types.all;
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/* Enable for synthesis; comment out for simulation.
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For this design, we just need boolean_vector. This is already included in Questa/ModelSim,
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but Quartus doesn't yet support this.
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*/
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use work.types.all;
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entity lfsr is generic(
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entity lfsr is generic(
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/*
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/*
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* Tap vector: a TRUE means that position is tapped, otherwise that position is untapped.
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* Tap vector: a TRUE means that position is tapped, otherwise that position is untapped.
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*/
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*/
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taps:boolean_vector
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taps:boolean_vector
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);
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);
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port(nReset,clk:in std_ulogic:='0';
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port(nReset,clk:in std_ulogic:='0';
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load:in boolean;
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load:in boolean;
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seed:in unsigned(taps'high downto 0);
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seed:in unsigned(taps'high downto 0);
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d:in std_ulogic;
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d:in std_ulogic;
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q:out unsigned(taps'high downto 0)
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q:out unsigned(taps'high downto 0)
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);
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);
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end entity lfsr;
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end entity lfsr;
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architecture rtl of lfsr is
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architecture rtl of lfsr is
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signal i_d,i_q:unsigned(taps'high downto 0);
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signal i_d,i_q:unsigned(taps'high downto 0);
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signal x:unsigned(taps'high-1 downto 0);
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signal x:unsigned(taps'high-1 downto 0);
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begin
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begin
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-- /* [begin]: Simulation testbench stimuli. Do not remove.
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-- /* [begin]: Simulation testbench stimuli. Do not remove.
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-- TODO migrate to separate testbench when more testcases are developed.
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-- TODO migrate to separate testbench when more testcases are developed.
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-- */
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-- */
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-- /* synthesis translate_off */
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-- /* synthesis translate_off */
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-- clk<=not clk after 1 ns;
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-- clk<=not clk after 1 ns;
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-- /* synthesis translate_on */
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-- /* synthesis translate_on */
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-- /* [end]: simulation stimuli. */
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-- /* [end]: simulation stimuli. */
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/* Receives a vector of taps; generates LFSR structure with correct XOR positionings. */
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/* Receives a vector of taps; generates LFSR structure with correct XOR positionings. */
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tapGenr: for i in 0 to taps'high-1 generate
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tapGenr: for i in 0 to taps'high-1 generate
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i_d(i+1)<=x(i) when taps(i) else i_q(i);
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i_d(i+1)<=x(i) when taps(i) else i_q(i);
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x(i)<=i_q(i) xor i_q(taps'high); -- when nReset else '0';
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x(i)<=i_q(i) xor i_q(taps'high);
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end generate;
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end generate;
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process(nReset,load,seed,clk) is begin
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process(nReset,load,seed,clk) is begin
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--if nReset='0' or load then i_q<=seed;
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if nReset='0' then i_q<=(others=>'0');
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if nReset='0' then i_q<=(others=>'0');
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elsif load then i_q<=seed;
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elsif load then i_q<=seed;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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i_q<=i_d;
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i_q<=i_d;
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end if;
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end if;
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end process;
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end process;
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i_d(0)<=d;
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i_d(0)<=d;
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q<=i_d;
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q<=i_d;
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end architecture rtl;
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end architecture rtl;
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