URL
https://opencores.org/ocsvn/generic_booth_multipler/generic_booth_multipler/trunk
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Alu is
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entity Alu is
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generic(
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size : integer:= 4
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);
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port(
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port(
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A : in std_logic_vector;
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A : in std_logic_vector(size-1 downto 0);
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B : in std_logic_vector;
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B : in std_logic_vector(size-1 downto 0);
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op : in std_logic;
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op : in std_logic;
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S : out std_logic_vector);
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S : out std_logic_vector(size-1 downto 0));
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end Alu;
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end Alu;
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architecture Behavioral of Alu is
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architecture Behavioral of Alu is
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component Adder is
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component Adder is
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generic(
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size : integer:= 4
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);
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port(
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port(
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A : in std_logic_vector;
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A : in std_logic_vector(size-1 downto 0);
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B : in std_logic_vector;
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B : in std_logic_vector(size-1 downto 0);
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Cin : in std_logic;
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Cin : in std_logic;
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S : out std_logic_vector;
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S : out std_logic_vector(size-1 downto 0);
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Cout : out std_logic);
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Cout : out std_logic);
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end component;
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end component;
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component XorCrearor is
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component XorCrearor is
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generic(
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size : integer:= 4
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);
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port(
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port(
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input1 : in std_logic;
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input1 : in std_logic;
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input2 : in std_logic_vector;
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input2 : in std_logic_vector(size-1 downto 0);
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result : out std_logic_vector);
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result : out std_logic_vector);
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end component;
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end component;
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signal xored: std_logic_vector(A'range);
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signal xored: std_logic_vector(A'range);
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begin
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begin
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XO :XorCrearor port map(op,B,xored);
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XO :XorCrearor
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ADD:ADDER port map(A,xored,op,S,open);
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generic map (
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size => size
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)
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port map(
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input1 => op,
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input2 =>B,
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result => xored);
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ADD: ADDER
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generic map (
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size => size
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)
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port map(
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A=> A,
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B=> xored,
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cin=> op,
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S=> S,
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cout=> open);
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end Behavioral;
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end Behavioral;
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