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[/] [generic_booth_multipler/] [trunk/] [rtl/] [modules/] [00.RightShiftReg.vhd] - Diff between revs 2 and 6

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library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
 
 
entity RightShiftReg is
entity RightShiftReg is
 
        generic(
 
                size : integer := 4
 
        );
        port(
        port(
                clock    :in    std_logic;
                clock    :in    std_logic;
                enable :in      std_logic;
                enable :in      std_logic;
                shift    :in    std_logic;
                shift    :in    std_logic;
                din      :in    std_logic_vector;
                din      :in    std_logic_vector(size-1 downto 0);
                dout     :out std_logic_vector(1 downto 0));
                dout     :out std_logic_vector(1 downto 0));
end RightShiftReg;
end RightShiftReg;
 
 
architecture Behavioral of RightShiftReg is
architecture Behavioral of RightShiftReg is
        signal data : std_logic_vector(din'length-1 downto 0);
        signal data : std_logic_vector(din'length-1 downto 0);

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