| Line 1... |
Line 1... |
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
|
entity BoothDatapath is
|
entity BoothDatapath is
|
|
generic(
|
|
size: integer := 4
|
|
);
|
port(
|
port(
|
clock :in std_logic;
|
clock :in std_logic;
|
reset :in std_logic;
|
reset :in std_logic;
|
load :in std_logic;
|
load :in std_logic;
|
shift :in std_logic;
|
shift :in std_logic;
|
X : in std_logic_vector;
|
X : in std_logic_vector(size-1 downto 0);
|
Y : in std_logic_vector;
|
Y : in std_logic_vector(size-1 downto 0);
|
P : out std_logic_vector);
|
P : out std_logic_vector(2*size-1 downto 0));
|
end BoothDatapath;
|
end BoothDatapath;
|
|
|
architecture Behavioral of BoothDatapath is
|
architecture Behavioral of BoothDatapath is
|
|
|
component Regeister is
|
component Regeister is
|
|
generic (
|
|
size: integer := 4
|
|
);
|
port(
|
port(
|
clock :in std_logic;
|
clock :in std_logic;
|
enable :in std_logic;
|
enable :in std_logic;
|
reset :in std_logic;
|
reset :in std_logic;
|
din :in std_logic_vector;
|
din :in std_logic_vector(size-1 downto 0);
|
dout :out std_logic_vector);
|
dout :out std_logic_vector(size-1 downto 0));
|
end component;
|
end component;
|
|
|
component LeftShiftReg is
|
component LeftShiftReg is
|
|
generic(
|
|
size : integer:= 4
|
|
);
|
port(
|
port(
|
clock :in std_logic;
|
clock :in std_logic;
|
enable :in std_logic;
|
enable :in std_logic;
|
shift :in std_logic;
|
shift :in std_logic;
|
din :in std_logic_vector;
|
din :in std_logic_vector(size-1 downto 0);
|
dout :out std_logic_vector);
|
dout :out std_logic_vector(size-1 downto 0));
|
end component;
|
end component;
|
|
|
component RightShiftReg is
|
component RightShiftReg is
|
|
generic(
|
|
size : integer := 4
|
|
);
|
port(
|
port(
|
clock : in std_logic;
|
clock : in std_logic;
|
enable : in std_logic;
|
enable : in std_logic;
|
shift : in std_logic;
|
shift : in std_logic;
|
din : in std_logic_vector;
|
din :in std_logic_vector(size-1 downto 0);
|
dout : out std_logic_vector(1 downto 0));
|
dout : out std_logic_vector(1 downto 0));
|
end component;
|
end component;
|
component BoothEncoder is
|
component BoothEncoder is
|
port(
|
port(
|
input1 : in std_logic;
|
input1 : in std_logic;
|
| Line 48... |
Line 60... |
product : out std_logic
|
product : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
component Alu is
|
component Alu is
|
|
generic(
|
|
size : integer:= 4
|
|
);
|
port(
|
port(
|
A : in std_logic_vector;
|
A : in std_logic_vector(size-1 downto 0);
|
B : in std_logic_vector;
|
B : in std_logic_vector(size-1 downto 0);
|
op : in std_logic;
|
op : in std_logic;
|
S : out std_logic_vector);
|
S : out std_logic_vector(size-1 downto 0));
|
end component;
|
end component;
|
component Ander is
|
component Ander is
|
|
generic(
|
|
size : integer:= 4
|
|
);
|
port(
|
port(
|
input1 : in std_logic;
|
input1 : in std_logic;
|
input2 : in std_logic_vector;
|
input2 : in std_logic_vector(size-1 downto 0);
|
result : out std_logic_vector);
|
result : out std_logic_vector(size-1 downto 0));
|
end component;
|
end component;
|
signal sign_extended_x,andout,alu_out,p_out,X_reg_dout: std_logic_vector(2*X'length -1 downto 0);
|
signal sign_extended_x,andout,alu_out,p_out,X_reg_dout: std_logic_vector(2*X'length -1 downto 0);
|
signal lessTwoBits : std_logic_vector(1 downto 0);
|
signal lessTwoBits : std_logic_vector(1 downto 0);
|
signal operator,product : std_logic;
|
signal operator,product : std_logic;
|
signal Y_concat_zero : std_logic_vector(y'length downto 0);
|
signal Y_concat_zero : std_logic_vector(y'length downto 0);
|
| Line 76... |
Line 94... |
input0=>lessTwoBits(0),
|
input0=>lessTwoBits(0),
|
operator => operator,
|
operator => operator,
|
product => product);
|
product => product);
|
|
|
Y_REG : RightShiftReg
|
Y_REG : RightShiftReg
|
|
generic map(size => size+1)
|
port map(
|
port map(
|
clock => clock,
|
clock => clock,
|
enable => load,
|
enable => load,
|
shift =>shift,
|
shift =>shift,
|
din => Y_concat_zero,
|
din => Y_concat_zero,
|
dout => lessTwoBits);
|
dout => lessTwoBits);
|
|
|
X_REG : LeftShiftReg
|
X_REG : LeftShiftReg
|
|
generic map(size => 2*size)
|
port map(
|
port map(
|
clock => clock,
|
clock => clock,
|
enable => load,
|
enable => load,
|
shift => shift,
|
shift => shift,
|
din => sign_extended_x,
|
din => sign_extended_x,
|
dout => X_reg_dout);
|
dout => X_reg_dout);
|
|
|
ANDing : Ander
|
ANDing : Ander
|
|
generic map(size => 2*size)
|
port map(
|
port map(
|
input1 => product,
|
input1 => product,
|
input2 => X_reg_dout,
|
input2 => X_reg_dout,
|
result => AndOut);
|
result => AndOut);
|
|
|
Add_Sub : ALU
|
Add_Sub : ALU
|
|
generic map(size => 2*size)
|
port map(
|
port map(
|
A => P_out,
|
A => P_out,
|
B => AndOut,
|
B => AndOut,
|
op => operator,
|
op => operator,
|
S => ALU_Out);
|
S => ALU_Out);
|
|
|
P_REG : Regeister
|
P_REG : Regeister
|
|
generic map(size => 2*size)
|
port map(
|
port map(
|
clock => clock,
|
clock => clock,
|
enable => shift,
|
enable => shift,
|
reset => reset,
|
reset => reset,
|
din => ALU_Out,
|
din => ALU_Out,
|
