URL
https://opencores.org/ocsvn/generic_booth_multipler/generic_booth_multipler/trunk
Show entire file |
Details |
Blame |
View Log
| Rev 2 |
Rev 6 |
| Line 15... |
Line 15... |
end BoothMultiplier;
|
end BoothMultiplier;
|
|
|
architecture Behavioral of BoothMultiplier is
|
architecture Behavioral of BoothMultiplier is
|
|
|
component counter is
|
component counter is
|
|
generic(
|
|
size: integer := 4
|
|
);
|
port( clock : in std_logic;
|
port( clock : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
value : out std_logic_vector);
|
value : out std_logic_vector);
|
end component counter;
|
end component counter;
|
|
|
component BoothDatapath is
|
component BoothDatapath is
|
|
generic(
|
|
size: integer := 4
|
|
);
|
port(
|
port(
|
clock :in std_logic;
|
clock :in std_logic;
|
reset :in std_logic;
|
reset :in std_logic;
|
load :in std_logic;
|
load :in std_logic;
|
shift :in std_logic;
|
shift :in std_logic;
|
| Line 56... |
Line 62... |
CONSTANT ONES : std_logic_vector(COUNTER_SIZE - 1 downto 0) := (others => '1');
|
CONSTANT ONES : std_logic_vector(COUNTER_SIZE - 1 downto 0) := (others => '1');
|
|
|
begin
|
begin
|
|
|
datapath: BoothDatapath
|
datapath: BoothDatapath
|
|
generic map(2**COUNTER_SIZE)
|
port map(
|
port map(
|
clock => clock,
|
clock => clock,
|
reset => reg_clear,
|
reset => reg_clear,
|
load => load,
|
load => load,
|
shift => shift,
|
shift => shift,
|
X => X_data,
|
X => X_data,
|
Y => Y_data,
|
Y => Y_data,
|
P => Result);
|
P => Result);
|
|
|
counter_unit: counter
|
counter_unit: counter
|
|
generic map(size => COUNTER_SIZE)
|
port map(
|
port map(
|
clock => clock,
|
clock => clock,
|
reset => cnt_clear,
|
reset => cnt_clear,
|
value => counter_value);
|
value => counter_value);
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.