--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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-- Entity: wrapperComponents
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-- Entity: wrapperComponents
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-- Date:2011-11-17
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-- Date:2011-11-17
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-- Author: apaluch
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-- Author: Andrzej Paluch
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--
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--
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-- Description ${cursor}
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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package wrapperComponents is
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package wrapperComponents is
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component RegsGpibFasade is
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component RegsGpibFasade is
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port (
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port (
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reset : std_logic;
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reset : std_logic;
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clk : in std_logic;
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clk : in std_logic;
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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------------ GPIB interface signals -----------------------------------
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------------ GPIB interface signals -----------------------------------
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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DI : in std_logic_vector (7 downto 0);
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DI : in std_logic_vector (7 downto 0);
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DO : out std_logic_vector (7 downto 0);
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DO : out std_logic_vector (7 downto 0);
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output_valid : out std_logic;
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output_valid : out std_logic;
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-- attention
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-- attention
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ATN_in : in std_logic;
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ATN_in : in std_logic;
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ATN_out : out std_logic;
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ATN_out : out std_logic;
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-- data valid
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-- data valid
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DAV_in : in std_logic;
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DAV_in : in std_logic;
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DAV_out : out std_logic;
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DAV_out : out std_logic;
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-- not ready for data
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-- not ready for data
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NRFD_in : in std_logic;
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NRFD_in : in std_logic;
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NRFD_out : out std_logic;
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NRFD_out : out std_logic;
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-- no data accepted
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-- no data accepted
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NDAC_in : in std_logic;
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NDAC_in : in std_logic;
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NDAC_out : out std_logic;
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NDAC_out : out std_logic;
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-- end or identify
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-- end or identify
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EOI_in : in std_logic;
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EOI_in : in std_logic;
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EOI_out : out std_logic;
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EOI_out : out std_logic;
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-- service request
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-- service request
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SRQ_in : in std_logic;
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SRQ_in : in std_logic;
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SRQ_out : out std_logic;
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SRQ_out : out std_logic;
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-- interface clear
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-- interface clear
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IFC_in : in std_logic;
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IFC_in : in std_logic;
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IFC_out : out std_logic;
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IFC_out : out std_logic;
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-- remote enable
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-- remote enable
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REN_in : in std_logic;
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REN_in : in std_logic;
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REN_out : out std_logic;
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REN_out : out std_logic;
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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---------------- registers access -------------------------------------
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---------------- registers access -------------------------------------
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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data_in : in std_logic_vector(15 downto 0);
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data_in : in std_logic_vector(15 downto 0);
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data_out : out std_logic_vector(15 downto 0);
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data_out : out std_logic_vector(15 downto 0);
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reg_addr : in std_logic_vector(14 downto 0);
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reg_addr : in std_logic_vector(14 downto 0);
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strobe_read : in std_logic;
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strobe_read : in std_logic;
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strobe_write : in std_logic;
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strobe_write : in std_logic;
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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---------------- additional lines -------------------------------------
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---------------- additional lines -------------------------------------
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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interrupt_line : out std_logic
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interrupt_line : out std_logic
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;debug1 : out std_logic
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;debug1 : out std_logic
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;debug2 : out std_logic
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;debug2 : out std_logic
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);
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);
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end component;
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end component;
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component InterruptGenerator is
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component InterruptGenerator is
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port (
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port (
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reset : std_logic;
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reset : std_logic;
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clk : in std_logic;
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clk : in std_logic;
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interrupt : out std_logic;
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interrupt : out std_logic;
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-------------------- gpib device ---------------------
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-------------------- gpib device ---------------------
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-- device is local controlled
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-- device is local controlled
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isLocal : in std_logic;
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isLocal : in std_logic;
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-- input buffer ready
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-- input buffer ready
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in_buf_ready : in std_logic;
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in_buf_ready : in std_logic;
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-- output buffer ready
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-- output buffer ready
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out_buf_ready : in std_logic;
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out_buf_ready : in std_logic;
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-- clear device (DC)
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-- clear device (DC)
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clr : in std_logic;
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clr : in std_logic;
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-- trigger device (DT)
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-- trigger device (DT)
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trg : in std_logic;
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trg : in std_logic;
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-- addressed to talk(L or LE)
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-- addressed to talk(L or LE)
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att : in std_logic;
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att : in std_logic;
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-- addressed to listen (T or TE)
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-- addressed to listen (T or TE)
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atl : in std_logic;
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atl : in std_logic;
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-- seriall poll active
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-- seriall poll active
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spa : in std_logic;
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spa : in std_logic;
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-------------------- gpib controller ---------------------
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-------------------- gpib controller ---------------------
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-- controller write commands
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-- controller write commands
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cwrc : in std_logic;
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cwrc : in std_logic;
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-- controller write data
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-- controller write data
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cwrd : in std_logic;
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cwrd : in std_logic;
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-- service requested
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-- service requested
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srq : in std_logic;
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srq : in std_logic;
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-- parallel poll ready
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-- parallel poll ready
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ppr : in std_logic;
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ppr : in std_logic;
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-- stb received
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-- stb received
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stb_received : in std_logic;
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stb_received : in std_logic;
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REN : in std_logic;
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REN : in std_logic;
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ATN : in std_logic;
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ATN : in std_logic;
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IFC : in std_logic
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IFC : in std_logic
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);
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);
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end component;
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end component;
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component RegMultiplexer is
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component RegMultiplexer is
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generic (
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generic (
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ADDR_WIDTH : integer := 15
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ADDR_WIDTH : integer := 15
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);
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);
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port (
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port (
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strobe_read : in std_logic;
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strobe_read : in std_logic;
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strobe_write : in std_logic;
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strobe_write : in std_logic;
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data_in : in std_logic_vector (15 downto 0);
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data_in : in std_logic_vector (15 downto 0);
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data_out : out std_logic_vector (15 downto 0);
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data_out : out std_logic_vector (15 downto 0);
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--------------------------------------------------------
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--------------------------------------------------------
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reg_addr : in std_logic_vector((ADDR_WIDTH-1) downto 0);
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reg_addr : in std_logic_vector((ADDR_WIDTH-1) downto 0);
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--------------------------------------------------------
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--------------------------------------------------------
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reg_strobe_0 : out std_logic;
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reg_strobe_0 : out std_logic;
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reg_in_0 : out std_logic_vector (15 downto 0);
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reg_in_0 : out std_logic_vector (15 downto 0);
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reg_out_0 : in std_logic_vector (15 downto 0);
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reg_out_0 : in std_logic_vector (15 downto 0);
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reg_strobe_1 : out std_logic;
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reg_strobe_1 : out std_logic;
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reg_in_1 : out std_logic_vector (15 downto 0);
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reg_in_1 : out std_logic_vector (15 downto 0);
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reg_out_1 : in std_logic_vector (15 downto 0);
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reg_out_1 : in std_logic_vector (15 downto 0);
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reg_strobe_2 : out std_logic;
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reg_strobe_2 : out std_logic;
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reg_in_2 : out std_logic_vector (15 downto 0);
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reg_in_2 : out std_logic_vector (15 downto 0);
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reg_out_2 : in std_logic_vector (15 downto 0);
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reg_out_2 : in std_logic_vector (15 downto 0);
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reg_strobe_3 : out std_logic;
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reg_strobe_3 : out std_logic;
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reg_in_3 : out std_logic_vector (15 downto 0);
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reg_in_3 : out std_logic_vector (15 downto 0);
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reg_out_3 : in std_logic_vector (15 downto 0);
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reg_out_3 : in std_logic_vector (15 downto 0);
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reg_strobe_4 : out std_logic;
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reg_strobe_4 : out std_logic;
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reg_in_4 : out std_logic_vector (15 downto 0);
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reg_in_4 : out std_logic_vector (15 downto 0);
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reg_out_4 : in std_logic_vector (15 downto 0);
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reg_out_4 : in std_logic_vector (15 downto 0);
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reg_strobe_5 : out std_logic;
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reg_strobe_5 : out std_logic;
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reg_in_5 : out std_logic_vector (15 downto 0);
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reg_in_5 : out std_logic_vector (15 downto 0);
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reg_out_5 : in std_logic_vector (15 downto 0);
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reg_out_5 : in std_logic_vector (15 downto 0);
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reg_strobe_6 : out std_logic;
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reg_strobe_6 : out std_logic;
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reg_in_6 : out std_logic_vector (15 downto 0);
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reg_in_6 : out std_logic_vector (15 downto 0);
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reg_out_6 : in std_logic_vector (15 downto 0);
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reg_out_6 : in std_logic_vector (15 downto 0);
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reg_strobe_7 : out std_logic;
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reg_strobe_7 : out std_logic;
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reg_in_7 : out std_logic_vector (15 downto 0);
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reg_in_7 : out std_logic_vector (15 downto 0);
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reg_out_7 : in std_logic_vector (15 downto 0);
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reg_out_7 : in std_logic_vector (15 downto 0);
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reg_strobe_8 : out std_logic;
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reg_strobe_8 : out std_logic;
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reg_in_8 : out std_logic_vector (15 downto 0);
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reg_in_8 : out std_logic_vector (15 downto 0);
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reg_out_8 : in std_logic_vector (15 downto 0);
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reg_out_8 : in std_logic_vector (15 downto 0);
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reg_strobe_9 : out std_logic;
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reg_strobe_9 : out std_logic;
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reg_in_9 : out std_logic_vector (15 downto 0);
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reg_in_9 : out std_logic_vector (15 downto 0);
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reg_out_9 : in std_logic_vector (15 downto 0);
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reg_out_9 : in std_logic_vector (15 downto 0);
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reg_strobe_10 : out std_logic;
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reg_strobe_10 : out std_logic;
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reg_in_10 : out std_logic_vector (15 downto 0);
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reg_in_10 : out std_logic_vector (15 downto 0);
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reg_out_10 : in std_logic_vector (15 downto 0);
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reg_out_10 : in std_logic_vector (15 downto 0);
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reg_strobe_11 : out std_logic;
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reg_strobe_11 : out std_logic;
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reg_in_11 : out std_logic_vector (15 downto 0);
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reg_in_11 : out std_logic_vector (15 downto 0);
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reg_out_11 : in std_logic_vector (15 downto 0);
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reg_out_11 : in std_logic_vector (15 downto 0);
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reg_strobe_other0 : out std_logic;
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reg_strobe_other0 : out std_logic;
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reg_in_other0 : out std_logic_vector (15 downto 0);
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reg_in_other0 : out std_logic_vector (15 downto 0);
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reg_out_other0 : in std_logic_vector (15 downto 0);
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reg_out_other0 : in std_logic_vector (15 downto 0);
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reg_strobe_other1 : out std_logic;
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reg_strobe_other1 : out std_logic;
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reg_in_other1 : out std_logic_vector (15 downto 0);
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reg_in_other1 : out std_logic_vector (15 downto 0);
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reg_out_other1 : in std_logic_vector (15 downto 0)
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reg_out_other1 : in std_logic_vector (15 downto 0)
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);
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);
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end component;
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end component;
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component EventReg is
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component EventReg is
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port (
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port (
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reset : in std_logic;
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reset : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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strobe : in std_logic;
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strobe : in std_logic;
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data_in : in std_logic_vector (15 downto 0);
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data_in : in std_logic_vector (15 downto 0);
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data_out : out std_logic_vector (15 downto 0);
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data_out : out std_logic_vector (15 downto 0);
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-------------------- gpib device ---------------------
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-------------------- gpib device ---------------------
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-- device is local controlled
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-- device is local controlled
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isLocal : in std_logic;
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isLocal : in std_logic;
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-- input buffer ready
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-- input buffer ready
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in_buf_ready : in std_logic;
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in_buf_ready : in std_logic;
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-- output buffer ready
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-- output buffer ready
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out_buf_ready : in std_logic;
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out_buf_ready : in std_logic;
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-- clear device (DC)
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-- clear device (DC)
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clr : in std_logic;
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clr : in std_logic;
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-- trigger device (DT)
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-- trigger device (DT)
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trg : in std_logic;
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trg : in std_logic;
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-- addressed to talk(L or LE)
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-- addressed to talk(L or LE)
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att : in std_logic;
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att : in std_logic;
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-- addressed to listen (T or TE)
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-- addressed to listen (T or TE)
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atl : in std_logic;
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atl : in std_logic;
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-- seriall poll active
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-- seriall poll active
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spa : in std_logic;
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spa : in std_logic;
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-------------------- gpib controller ---------------------
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-------------------- gpib controller ---------------------
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-- controller write commands
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-- controller write commands
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cwrc : in std_logic;
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cwrc : in std_logic;
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-- controller write data
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-- controller write data
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cwrd : in std_logic;
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cwrd : in std_logic;
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-- service requested
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-- service requested
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srq : in std_logic;
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srq : in std_logic;
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-- parallel poll ready
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-- parallel poll ready
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ppr : in std_logic;
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ppr : in std_logic;
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-- stb received
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-- stb received
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stb_received : in std_logic;
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stb_received : in std_logic;
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REN : in std_logic;
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REN : in std_logic;
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ATN : in std_logic;
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ATN : in std_logic;
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IFC : in std_logic
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IFC : in std_logic
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);
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);
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end component;
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end component;
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component gpibBusReg is
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component gpibBusReg is
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port (
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port (
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data_out : out std_logic_vector (15 downto 0);
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data_out : out std_logic_vector (15 downto 0);
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------------------------------------------------
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------------------------------------------------
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-- interface signals
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-- interface signals
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DIO : in std_logic_vector (7 downto 0);
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DIO : in std_logic_vector (7 downto 0);
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-- attention
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-- attention
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ATN : in std_logic;
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ATN : in std_logic;
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-- data valid
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-- data valid
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DAV : in std_logic;
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DAV : in std_logic;
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-- not ready for data
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-- not ready for data
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NRFD : in std_logic;
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NRFD : in std_logic;
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-- no data accepted
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-- no data accepted
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NDAC : in std_logic;
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NDAC : in std_logic;
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-- end or identify
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-- end or identify
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EOI : in std_logic;
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EOI : in std_logic;
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-- service request
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-- service request
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SRQ : in std_logic;
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SRQ : in std_logic;
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-- interface clear
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-- interface clear
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IFC : in std_logic;
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IFC : in std_logic;
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-- remote enable
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-- remote enable
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REN : in std_logic
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REN : in std_logic
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);
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);
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end component;
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end component;
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component gpibControlReg is
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component gpibControlReg is
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port (
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port (
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reset : in std_logic;
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reset : in std_logic;
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strobe : in std_logic;
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strobe : in std_logic;
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data_in : in std_logic_vector (15 downto 0);
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data_in : in std_logic_vector (15 downto 0);
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data_out : out std_logic_vector (15 downto 0);
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data_out : out std_logic_vector (15 downto 0);
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------------------ gpib ------------------------
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------------------ gpib ------------------------
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ltn : out std_logic; -- listen (L, LE)
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ltn : out std_logic; -- listen (L, LE)
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lun : out std_logic; -- local unlisten (L, LE)
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lun : out std_logic; -- local unlisten (L, LE)
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rtl : out std_logic; -- return to local (RL)
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rtl : out std_logic; -- return to local (RL)
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rsv : out std_logic; -- request service (SR)
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rsv : out std_logic; -- request service (SR)
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ist : out std_logic; -- individual status (PP)
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ist : out std_logic; -- individual status (PP)
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lpe : out std_logic; -- local poll enable (PP)
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lpe : out std_logic; -- local poll enable (PP)
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------------------------------------------------
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------------------------------------------------
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rsc : out std_logic; -- request system control (C)
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rsc : out std_logic; -- request system control (C)
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sic : out std_logic; -- send interface clear (C)
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sic : out std_logic; -- send interface clear (C)
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sre : out std_logic; -- send remote enable (C)
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sre : out std_logic; -- send remote enable (C)
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gts : out std_logic; -- go to standby (C)
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gts : out std_logic; -- go to standby (C)
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tcs : out std_logic; -- take control synchronously (C, AH)
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tcs : out std_logic; -- take control synchronously (C, AH)
|
tca : out std_logic; -- take control asynchronously (C)
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tca : out std_logic; -- take control asynchronously (C)
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rpp : out std_logic; -- request parallel poll (C)
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rpp : out std_logic; -- request parallel poll (C)
|
rec_stb : out std_logic -- receives status byte (C)
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rec_stb : out std_logic -- receives status byte (C)
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);
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);
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end component;
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end component;
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|
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component GpibStatusReg is
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component GpibStatusReg is
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port (
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port (
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data_out : out std_logic_vector (15 downto 0);
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data_out : out std_logic_vector (15 downto 0);
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-- gpib
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-- gpib
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currentSecAddr : in std_logic_vector (4 downto 0); -- current sec addr
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currentSecAddr : in std_logic_vector (4 downto 0); -- current sec addr
|
att : in std_logic; -- addressed to talk(L or LE)
|
att : in std_logic; -- addressed to talk(L or LE)
|
tac : in std_logic; -- talker active (T, TE)
|
tac : in std_logic; -- talker active (T, TE)
|
atl : in std_logic; -- addressed to listen (T or TE)
|
atl : in std_logic; -- addressed to listen (T or TE)
|
lac : in std_logic; -- listener active (L, LE)
|
lac : in std_logic; -- listener active (L, LE)
|
cwrc : in std_logic; -- controller write commands
|
cwrc : in std_logic; -- controller write commands
|
cwrd : in std_logic; -- controller write data
|
cwrd : in std_logic; -- controller write data
|
spa : in std_logic; -- seriall poll active
|
spa : in std_logic; -- seriall poll active
|
isLocal : in std_logic -- device is local controlled
|
isLocal : in std_logic -- device is local controlled
|
);
|
);
|
end component;
|
end component;
|
|
|
component ReaderControlReg0 is
|
component ReaderControlReg0 is
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
strobe : in std_logic;
|
strobe : in std_logic;
|
data_in : in std_logic_vector (15 downto 0);
|
data_in : in std_logic_vector (15 downto 0);
|
data_out : out std_logic_vector (15 downto 0);
|
data_out : out std_logic_vector (15 downto 0);
|
------------------- gpib -------------------------
|
------------------- gpib -------------------------
|
-- buffer ready interrupt
|
-- buffer ready interrupt
|
buf_interrupt : in std_logic;
|
buf_interrupt : in std_logic;
|
-- at least one byte available
|
-- at least one byte available
|
data_available : in std_logic;
|
data_available : in std_logic;
|
-- indicates end of stream
|
-- indicates end of stream
|
end_of_stream : in std_logic;
|
end_of_stream : in std_logic;
|
-- resets buffer
|
-- resets buffer
|
reset_buffer : out std_logic;
|
reset_buffer : out std_logic;
|
-- secondary address of data
|
-- secondary address of data
|
dataSecAddr : in std_logic_vector (4 downto 0)
|
dataSecAddr : in std_logic_vector (4 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component ReaderControlReg1 is
|
component ReaderControlReg1 is
|
port (
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port (
|
data_out : out std_logic_vector (15 downto 0);
|
data_out : out std_logic_vector (15 downto 0);
|
------------------ gpib --------------------
|
------------------ gpib --------------------
|
-- num of bytes available in fifo
|
-- num of bytes available in fifo
|
bytes_available_in_fifo : in std_logic_vector (10 downto 0)
|
bytes_available_in_fifo : in std_logic_vector (10 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component SecAddrReg is
|
component SecAddrReg is
|
port (
|
port (
|
reset : in std_logic;
|
reset : in std_logic;
|
strobe : in std_logic;
|
strobe : in std_logic;
|
data_in : in std_logic_vector (15 downto 0);
|
data_in : in std_logic_vector (15 downto 0);
|
data_out : out std_logic_vector (15 downto 0);
|
data_out : out std_logic_vector (15 downto 0);
|
-- gpib
|
-- gpib
|
secAddrMask : out std_logic_vector (15 downto 0)
|
secAddrMask : out std_logic_vector (15 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component SettingsReg0 is
|
component SettingsReg0 is
|
port (
|
port (
|
reset : in std_logic;
|
reset : in std_logic;
|
strobe : in std_logic;
|
strobe : in std_logic;
|
data_in : in std_logic_vector (15 downto 0);
|
data_in : in std_logic_vector (15 downto 0);
|
data_out : out std_logic_vector (15 downto 0);
|
data_out : out std_logic_vector (15 downto 0);
|
------------- gpib -----------------------------
|
------------- gpib -----------------------------
|
isLE_TE : out std_logic;
|
isLE_TE : out std_logic;
|
lpeUsed : out std_logic;
|
lpeUsed : out std_logic;
|
fixedPpLine : out std_logic_vector (2 downto 0);
|
fixedPpLine : out std_logic_vector (2 downto 0);
|
eosUsed : out std_logic;
|
eosUsed : out std_logic;
|
eosMark : out std_logic_vector (7 downto 0);
|
eosMark : out std_logic_vector (7 downto 0);
|
lon : out std_logic;
|
lon : out std_logic;
|
ton : out std_logic
|
ton : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
component SettingsReg1 is
|
component SettingsReg1 is
|
port (
|
port (
|
reset : in std_logic;
|
reset : in std_logic;
|
strobe : in std_logic;
|
strobe : in std_logic;
|
data_in : in std_logic_vector (15 downto 0);
|
data_in : in std_logic_vector (15 downto 0);
|
data_out : out std_logic_vector (15 downto 0);
|
data_out : out std_logic_vector (15 downto 0);
|
-- gpib
|
-- gpib
|
myAddr : out std_logic_vector (4 downto 0);
|
myAddr : out std_logic_vector (4 downto 0);
|
T1 : out std_logic_vector (7 downto 0)
|
T1 : out std_logic_vector (7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component WriterControlReg0 is
|
component WriterControlReg0 is
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
strobe : in std_logic;
|
strobe : in std_logic;
|
data_in : in std_logic_vector (15 downto 0);
|
data_in : in std_logic_vector (15 downto 0);
|
data_out : out std_logic_vector (15 downto 0);
|
data_out : out std_logic_vector (15 downto 0);
|
------------------- gpib -------------------------
|
------------------- gpib -------------------------
|
-- buffer consumed
|
-- buffer consumed
|
buf_interrupt : in std_logic;
|
buf_interrupt : in std_logic;
|
-- data avilable - at least one byte in buffer
|
-- data avilable - at least one byte in buffer
|
data_available : out std_logic;
|
data_available : out std_logic;
|
-- indicates end of stream
|
-- indicates end of stream
|
end_of_stream : out std_logic;
|
end_of_stream : out std_logic;
|
-- resets buffer
|
-- resets buffer
|
reset_buffer : out std_logic;
|
reset_buffer : out std_logic;
|
-- secondary address of data
|
-- secondary address of data
|
dataSecAddr : out std_logic_vector (4 downto 0);
|
dataSecAddr : out std_logic_vector (4 downto 0);
|
-- serial poll status byte
|
-- serial poll status byte
|
status_byte : out std_logic_vector (6 downto 0)
|
status_byte : out std_logic_vector (6 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component WriterControlReg1 is
|
component WriterControlReg1 is
|
port (
|
port (
|
reset : in std_logic;
|
reset : in std_logic;
|
strobe : in std_logic;
|
strobe : in std_logic;
|
data_in : in std_logic_vector (15 downto 0);
|
data_in : in std_logic_vector (15 downto 0);
|
data_out : out std_logic_vector (15 downto 0);
|
data_out : out std_logic_vector (15 downto 0);
|
------------------ gpib --------------------
|
------------------ gpib --------------------
|
-- num of bytes available in fifo
|
-- num of bytes available in fifo
|
bytes_available_in_fifo : in std_logic_vector (10 downto 0)
|
bytes_available_in_fifo : in std_logic_vector (10 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
end wrapperComponents;
|
end wrapperComponents;
|
|
|
|
|
