|
--------------------------------------------------------------------------------
|
|
--This file is part of fpga_gpib_controller.
|
|
--
|
|
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
|
|
-- it under the terms of the GNU General Public License as published by
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
|
-- (at your option) any later version.
|
|
--
|
|
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
-- GNU General Public License for more details.
|
|
|
|
-- You should have received a copy of the GNU General Public License
|
|
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
-- Company:
|
-- Author: Andrzej Paluch
|
-- Engineer:
|
|
--
|
--
|
-- Create Date: 01:04:57 10/03/2011
|
-- Create Date: 01:04:57 10/03/2011
|
-- Design Name:
|
-- Design Name:
|
-- Module Name: if_func_PP - Behavioral
|
-- Module Name: if_func_PP - Behavioral
|
-- Project Name:
|
-- Project Name:
|
-- Target Devices:
|
-- Target Devices:
|
-- Tool versions:
|
-- Tool versions:
|
-- Description:
|
-- Description:
|
--
|
--
|
-- Dependencies:
|
-- Dependencies:
|
--
|
--
|
-- Revision:
|
-- Revision:
|
-- Revision 0.01 - File Created
|
-- Revision 0.01 - File Created
|
-- Additional Comments:
|
-- Additional Comments:
|
--
|
--
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
|
use work.utilPkg.all;
|
use work.utilPkg.all;
|
|
|
entity if_func_PP is
|
entity if_func_PP is
|
port(
|
port(
|
-- device inputs
|
-- device inputs
|
clk : in std_logic; -- clock
|
clk : in std_logic; -- clock
|
-- settings
|
-- settings
|
lpeUsed : std_logic;
|
lpeUsed : std_logic;
|
fixedPpLine : in std_logic_vector (2 downto 0);
|
fixedPpLine : in std_logic_vector (2 downto 0);
|
-- local commands
|
-- local commands
|
pon : in std_logic; -- power on
|
pon : in std_logic; -- power on
|
lpe : in std_logic; -- local poll enable
|
lpe : in std_logic; -- local poll enable
|
ist : in std_logic; -- individual status
|
ist : in std_logic; -- individual status
|
-- state inputs
|
-- state inputs
|
ACDS : in std_logic; -- accept data state
|
ACDS : in std_logic; -- accept data state
|
LADS : in std_logic; -- listener address state (L or LE)
|
LADS : in std_logic; -- listener address state (L or LE)
|
-- data input
|
-- data input
|
dio_data : in std_logic_vector(3 downto 0); -- byte from data lines
|
dio_data : in std_logic_vector(3 downto 0); -- byte from data lines
|
-- remote command inputs
|
-- remote command inputs
|
IDY : in std_logic; -- identify
|
IDY : in std_logic; -- identify
|
PPE : in std_logic; -- parallel poll enable
|
PPE : in std_logic; -- parallel poll enable
|
PPD : in std_logic; -- parallel poll disable
|
PPD : in std_logic; -- parallel poll disable
|
PPC : in std_logic; -- parallel poll configure
|
PPC : in std_logic; -- parallel poll configure
|
PPU : in std_logic; -- parallel poll unconfigure
|
PPU : in std_logic; -- parallel poll unconfigure
|
PCG : in std_logic; -- primary command group
|
PCG : in std_logic; -- primary command group
|
-- remote command outputs
|
-- remote command outputs
|
PPR : out std_logic; -- paralel poll response
|
PPR : out std_logic; -- paralel poll response
|
-- PPR command data
|
-- PPR command data
|
ppBitValue : out std_logic; -- bit value
|
ppBitValue : out std_logic; -- bit value
|
ppLineNumber : out std_logic_vector (2 downto 0);
|
ppLineNumber : out std_logic_vector (2 downto 0);
|
-- reported states
|
-- reported states
|
PPAS : out std_logic -- parallel poll active state
|
PPAS : out std_logic -- parallel poll active state
|
);
|
);
|
end if_func_PP;
|
end if_func_PP;
|
|
|
architecture Behavioral of if_func_PP is
|
architecture Behavioral of if_func_PP is
|
|
|
-- states
|
-- states
|
type PP_STATE_1 is (
|
type PP_STATE_1 is (
|
-- parallel poll idle state
|
-- parallel poll idle state
|
ST_PPIS,
|
ST_PPIS,
|
-- parallel poll standby state
|
-- parallel poll standby state
|
ST_PPSS,
|
ST_PPSS,
|
-- parallel poll active state
|
-- parallel poll active state
|
ST_PPAS
|
ST_PPAS
|
);
|
);
|
|
|
-- states
|
-- states
|
type PP_STATE_2 is (
|
type PP_STATE_2 is (
|
-- parallel poll unaddressed to configure state
|
-- parallel poll unaddressed to configure state
|
ST_PUCS,
|
ST_PUCS,
|
-- parallel poll addressed to configure state
|
-- parallel poll addressed to configure state
|
ST_PACS
|
ST_PACS
|
);
|
);
|
|
|
-- current state
|
-- current state
|
signal current_state_1 : PP_STATE_1;
|
signal current_state_1 : PP_STATE_1;
|
signal current_state_2 : PP_STATE_2;
|
signal current_state_2 : PP_STATE_2;
|
|
|
-- predicates
|
-- predicates
|
signal pred1, pred2, pred3, pred4, pred5 : boolean;
|
signal pred1, pred2, pred3, pred4, pred5 : boolean;
|
|
|
-- memorized PP metadata
|
-- memorized PP metadata
|
signal S : std_logic;
|
signal S : std_logic;
|
signal lineAddr : std_logic_vector (2 downto 0);
|
signal lineAddr : std_logic_vector (2 downto 0);
|
|
|
begin
|
begin
|
|
|
-- state machine process - PP_STATE_1
|
-- state machine process - PP_STATE_1
|
process(pon, clk) begin
|
process(pon, clk) begin
|
if pon = '1' then
|
if pon = '1' then
|
current_state_1 <= ST_PPIS;
|
current_state_1 <= ST_PPIS;
|
elsif rising_edge(clk) then
|
elsif rising_edge(clk) then
|
case current_state_1 is
|
case current_state_1 is
|
------------------
|
------------------
|
when ST_PPIS =>
|
when ST_PPIS =>
|
if pred1 then
|
if pred1 then
|
S <= dio_data(3);
|
S <= dio_data(3);
|
lineAddr <= dio_data(2 downto 0);
|
lineAddr <= dio_data(2 downto 0);
|
current_state_1 <= ST_PPSS;
|
current_state_1 <= ST_PPSS;
|
end if;
|
end if;
|
------------------
|
------------------
|
when ST_PPSS =>
|
when ST_PPSS =>
|
if pred3 then
|
if pred3 then
|
current_state_1 <= ST_PPAS;
|
current_state_1 <= ST_PPAS;
|
elsif pred2 then
|
elsif pred2 then
|
current_state_1 <= ST_PPIS;
|
current_state_1 <= ST_PPIS;
|
end if;
|
end if;
|
------------------
|
------------------
|
when ST_PPAS =>
|
when ST_PPAS =>
|
if not pred3 then
|
if not pred3 then
|
current_state_1 <= ST_PPSS;
|
current_state_1 <= ST_PPSS;
|
end if;
|
end if;
|
------------------
|
------------------
|
when others =>
|
when others =>
|
current_state_1 <= ST_PPIS;
|
current_state_1 <= ST_PPIS;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- state machine process - PP_STATE_2
|
-- state machine process - PP_STATE_2
|
process(pon, clk) begin
|
process(pon, clk) begin
|
if pon = '1' then
|
if pon = '1' then
|
current_state_2 <= ST_PUCS;
|
current_state_2 <= ST_PUCS;
|
elsif rising_edge(clk) then
|
elsif rising_edge(clk) then
|
case current_state_2 is
|
case current_state_2 is
|
------------------
|
------------------
|
when ST_PUCS =>
|
when ST_PUCS =>
|
if pred4 then
|
if pred4 then
|
current_state_2 <= ST_PACS;
|
current_state_2 <= ST_PACS;
|
end if;
|
end if;
|
------------------
|
------------------
|
when ST_PACS =>
|
when ST_PACS =>
|
if pred5 then
|
if pred5 then
|
current_state_2 <= ST_PUCS;
|
current_state_2 <= ST_PUCS;
|
end if;
|
end if;
|
------------------
|
------------------
|
when others =>
|
when others =>
|
current_state_2 <= ST_PUCS;
|
current_state_2 <= ST_PUCS;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
ppBitValue <= (not S xor ist) when lpeUsed='0' else ist;
|
ppBitValue <= (not S xor ist) when lpeUsed='0' else ist;
|
ppLineNumber <= lineAddr when lpeUsed='0' else fixedPpLine;
|
ppLineNumber <= lineAddr when lpeUsed='0' else fixedPpLine;
|
PPR <= to_stdl(current_state_1 = ST_PPAS);
|
PPR <= to_stdl(current_state_1 = ST_PPAS);
|
PPAS <= to_stdl(current_state_1 = ST_PPAS);
|
PPAS <= to_stdl(current_state_1 = ST_PPAS);
|
|
|
-- predicates
|
-- predicates
|
with lpeUsed select
|
with lpeUsed select
|
pred1 <=
|
pred1 <=
|
is_1(lpe) when '1',
|
is_1(lpe) when '1',
|
PPE='1' and current_state_2=ST_PACS and ACDS='1' when others;
|
PPE='1' and current_state_2=ST_PACS and ACDS='1' when others;
|
|
|
with lpeUsed select
|
with lpeUsed select
|
pred2 <=
|
pred2 <=
|
is_1(not lpe) when '1',
|
is_1(not lpe) when '1',
|
((PPD='1' and current_state_2=ST_PACS) or PPU='1') and ACDS='1'
|
((PPD='1' and current_state_2=ST_PACS) or PPU='1') and ACDS='1'
|
when others;
|
when others;
|
|
|
pred3 <= IDY='1';
|
pred3 <= IDY='1';
|
pred4 <= PPC='1' and LADS='1' and ACDS='1';
|
pred4 <= PPC='1' and LADS='1' and ACDS='1';
|
pred5 <= PCG='1' and PPC='0' and ACDS='1';
|
pred5 <= PCG='1' and PPC='0' and ACDS='1';
|
|
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|