--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--This file is part of fpga_gpib_controller.
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--
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-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- Fpga_gpib_controller is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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-- Entity: Fifo8b
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-- Entity: Fifo8b
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-- Date:2011-11-28
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-- Date:2011-11-28
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-- Author: Administrator
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-- Author: Andrzej Paluch
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--
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--
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-- Description ${cursor}
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-- Description ${cursor}
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use work.utilPkg.all;
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use work.utilPkg.all;
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use work.helperComponents.all;
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use work.helperComponents.all;
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entity Fifo8b is
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entity Fifo8b is
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generic (
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generic (
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MAX_ADDR_BIT_NUM : integer := 10
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MAX_ADDR_BIT_NUM : integer := 10
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);
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);
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port (
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port (
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reset : in std_logic;
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reset : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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-------------- fifo --------------------
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-------------- fifo --------------------
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bytesAvailable : out std_logic;
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bytesAvailable : out std_logic;
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availableBytesCount : out std_logic_vector(MAX_ADDR_BIT_NUM downto 0);
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availableBytesCount : out std_logic_vector(MAX_ADDR_BIT_NUM downto 0);
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bufferFull : out std_logic;
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bufferFull : out std_logic;
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resetFifo : in std_logic;
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resetFifo : in std_logic;
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----------------------------------------
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----------------------------------------
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data_in : in std_logic_vector(7 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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ready_to_write :out std_logic;
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ready_to_write :out std_logic;
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strobe_write : in std_logic;
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strobe_write : in std_logic;
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----------------------------------------
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----------------------------------------
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data_out : out std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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ready_to_read : out std_logic;
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ready_to_read : out std_logic;
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strobe_read : in std_logic
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strobe_read : in std_logic
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);
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);
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end Fifo8b;
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end Fifo8b;
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architecture arch of Fifo8b is
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architecture arch of Fifo8b is
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constant ADDR_BITS_COUNT : integer := MAX_ADDR_BIT_NUM + 1;
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constant ADDR_BITS_COUNT : integer := MAX_ADDR_BIT_NUM + 1;
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constant MEMORY_CELLS_COUNT : integer := 2**ADDR_BITS_COUNT;
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constant MEMORY_CELLS_COUNT : integer := 2**ADDR_BITS_COUNT;
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constant MAX_DATA_LENGTH : integer := MEMORY_CELLS_COUNT - 1;
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constant MAX_DATA_LENGTH : integer := MEMORY_CELLS_COUNT - 1;
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constant MAX_ADDR : integer := MAX_DATA_LENGTH;
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constant MAX_ADDR : integer := MAX_DATA_LENGTH;
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-------------- memory ----------------
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-------------- memory ----------------
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signal n_clk : std_logic;
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signal n_clk : std_logic;
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signal p1_addr : std_logic_vector(MAX_ADDR_BIT_NUM downto 0);
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signal p1_addr : std_logic_vector(MAX_ADDR_BIT_NUM downto 0);
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signal p1_data_in : std_logic_vector(7 downto 0);
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signal p1_data_in : std_logic_vector(7 downto 0);
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signal p1_strobe : std_logic;
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signal p1_strobe : std_logic;
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signal p1_data_out : std_logic_vector(7 downto 0);
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signal p1_data_out : std_logic_vector(7 downto 0);
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-------------------------------------------------
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-------------------------------------------------
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signal p2_addr : std_logic_vector(MAX_ADDR_BIT_NUM downto 0);
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signal p2_addr : std_logic_vector(MAX_ADDR_BIT_NUM downto 0);
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signal p2_data_in : std_logic_vector(7 downto 0);
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signal p2_data_in : std_logic_vector(7 downto 0);
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signal p2_strobe : std_logic;
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signal p2_strobe : std_logic;
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signal p2_data_out : std_logic_vector(7 downto 0);
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signal p2_data_out : std_logic_vector(7 downto 0);
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------------- fifo --------------------
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------------- fifo --------------------
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signal writeAddr : integer range 0 to MAX_ADDR;
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signal writeAddr : integer range 0 to MAX_ADDR;
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signal readAddr : integer range 0 to MAX_ADDR;
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signal readAddr : integer range 0 to MAX_ADDR;
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signal readAddrValid : std_logic;
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signal readAddrValid : std_logic;
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signal currentDataLen : integer range 0 to MAX_DATA_LENGTH;
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signal currentDataLen : integer range 0 to MAX_DATA_LENGTH;
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-------- control ----------------------
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-------- control ----------------------
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signal ss_r, sr_r, ss_w, sr_w : std_logic;
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signal ss_r, sr_r, ss_w, sr_w : std_logic;
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begin
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begin
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n_clk <= not clk;
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n_clk <= not clk;
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p2_strobe <= '0';
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p2_strobe <= '0';
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ready_to_write <= to_stdl((ss_w = sr_w) and currentDataLen < MAX_DATA_LENGTH);
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ready_to_write <= to_stdl((ss_w = sr_w) and currentDataLen < MAX_DATA_LENGTH);
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ready_to_read <= to_stdl((ss_r = sr_r) and currentDataLen > 0);
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ready_to_read <= to_stdl((ss_r = sr_r) and currentDataLen > 0);
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bytesAvailable <= to_stdl(currentDataLen > 0);
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bytesAvailable <= to_stdl(currentDataLen > 0);
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availableBytesCount <= conv_std_logic_vector(currentDataLen, ADDR_BITS_COUNT);
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availableBytesCount <= conv_std_logic_vector(currentDataLen, ADDR_BITS_COUNT);
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p1_data_in <= data_in;
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p1_data_in <= data_in;
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data_out <= p2_data_out;
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data_out <= p2_data_out;
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bufferFull <= to_stdl(currentDataLen = MAX_DATA_LENGTH);
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bufferFull <= to_stdl(currentDataLen = MAX_DATA_LENGTH);
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p1_addr <= conv_std_logic_vector(writeAddr, ADDR_BITS_COUNT);
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p1_addr <= conv_std_logic_vector(writeAddr, ADDR_BITS_COUNT);
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p2_addr <= conv_std_logic_vector(readAddr, ADDR_BITS_COUNT);
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p2_addr <= conv_std_logic_vector(readAddr, ADDR_BITS_COUNT);
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process (reset, clk) begin
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process (reset, clk) begin
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if reset = '1' then
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if reset = '1' then
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writeAddr <= 1;
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writeAddr <= 1;
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readAddr <= 0;
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readAddr <= 0;
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readAddrValid <= '0';
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readAddrValid <= '0';
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sr_w <= '0';
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sr_w <= '0';
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sr_r <= '0';
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sr_r <= '0';
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p1_strobe <= '0';
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p1_strobe <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if resetFifo = '1' then
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if resetFifo = '1' then
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writeAddr <= 1;
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writeAddr <= 1;
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readAddr <= 0;
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readAddr <= 0;
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readAddrValid <= '0';
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readAddrValid <= '0';
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sr_w <= ss_w;
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sr_w <= ss_w;
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sr_r <= ss_r;
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sr_r <= ss_r;
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p1_strobe <= '0';
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p1_strobe <= '0';
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else
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else
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if sr_w /= ss_w and currentDataLen < MAX_DATA_LENGTH and
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if sr_w /= ss_w and currentDataLen < MAX_DATA_LENGTH and
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p1_strobe = '0' then
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p1_strobe = '0' then
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p1_strobe <= '1';
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p1_strobe <= '1';
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elsif sr_w /= ss_w and currentDataLen < MAX_DATA_LENGTH and
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elsif sr_w /= ss_w and currentDataLen < MAX_DATA_LENGTH and
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p1_strobe = '1' then
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p1_strobe = '1' then
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p1_strobe <= '0';
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p1_strobe <= '0';
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sr_w <= ss_w;
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sr_w <= ss_w;
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if writeAddr < MAX_ADDR then
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if writeAddr < MAX_ADDR then
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writeAddr <= writeAddr + 1;
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writeAddr <= writeAddr + 1;
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else
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else
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writeAddr <= 0;
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writeAddr <= 0;
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end if;
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end if;
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if readAddrValid = '0' then
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if readAddrValid = '0' then
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if readAddr < MAX_ADDR then
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if readAddr < MAX_ADDR then
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readAddr <= readAddr + 1;
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readAddr <= readAddr + 1;
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else
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else
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readAddr <= 0;
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readAddr <= 0;
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end if;
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end if;
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readAddrValid <= '1';
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readAddrValid <= '1';
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end if;
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end if;
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end if;
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end if;
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if sr_r /= ss_r and currentDataLen > 0 and
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if sr_r /= ss_r and currentDataLen > 0 and
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readAddrValid = '1' then
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readAddrValid = '1' then
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sr_r <= ss_r;
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sr_r <= ss_r;
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if currentDataLen = 1 and
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if currentDataLen = 1 and
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-- and last writing phase is not ongoing
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-- and last writing phase is not ongoing
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not(sr_w /= ss_w and p1_strobe = '1') then
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not(sr_w /= ss_w and p1_strobe = '1') then
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-- if writing is not ongoing
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-- if writing is not ongoing
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readAddrValid <= '0';
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readAddrValid <= '0';
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else
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else
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if readAddr < MAX_ADDR then
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if readAddr < MAX_ADDR then
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readAddr <= readAddr + 1;
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readAddr <= readAddr + 1;
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else
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else
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readAddr <= 0;
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readAddr <= 0;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- calculate current length
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-- calculate current length
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process(writeAddr, readAddr, readAddrValid) begin
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process(writeAddr, readAddr, readAddrValid) begin
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if readAddrValid = '0' then
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if readAddrValid = '0' then
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currentDataLen <= 0;
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currentDataLen <= 0;
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elsif readAddr < writeAddr then
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elsif readAddr < writeAddr then
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currentDataLen <= writeAddr - readAddr;
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currentDataLen <= writeAddr - readAddr;
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else -- readAddr > writeAddr, readAddr = writeAddr shoud never happen
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else -- readAddr > writeAddr, readAddr = writeAddr shoud never happen
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currentDataLen <= (MEMORY_CELLS_COUNT - readAddr) + writeAddr;
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currentDataLen <= (MEMORY_CELLS_COUNT - readAddr) + writeAddr;
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end if;
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end if;
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end process;
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end process;
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-- subscribe write
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-- subscribe write
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process (reset, strobe_write) begin
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process (reset, strobe_write) begin
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if reset = '1' then
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if reset = '1' then
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ss_w <= '0';
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ss_w <= '0';
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elsif rising_edge(strobe_write) then
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elsif rising_edge(strobe_write) then
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if ss_w = sr_w then
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if ss_w = sr_w then
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ss_w <= not sr_w;
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ss_w <= not sr_w;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- subscribe read
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-- subscribe read
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process (reset, strobe_read) begin
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process (reset, strobe_read) begin
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if reset = '1' then
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if reset = '1' then
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ss_r <= '0';
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ss_r <= '0';
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elsif rising_edge(strobe_read) then
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elsif rising_edge(strobe_read) then
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if ss_r = sr_r then
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if ss_r = sr_r then
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ss_r <= not sr_r;
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ss_r <= not sr_r;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- target memory
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-- target memory
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mb: MemoryBlock port map (
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mb: MemoryBlock port map (
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reset => reset,
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reset => reset,
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clk => n_clk,
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clk => n_clk,
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-------------------------------------------------
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-------------------------------------------------
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p1_addr => p1_addr,
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p1_addr => p1_addr,
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p1_data_in => p1_data_in,
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p1_data_in => p1_data_in,
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p1_strobe => p1_strobe,
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p1_strobe => p1_strobe,
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p1_data_out => p1_data_out,
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p1_data_out => p1_data_out,
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-------------------------------------------------
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-------------------------------------------------
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p2_addr => p2_addr,
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p2_addr => p2_addr,
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p2_data_in => p2_data_in,
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p2_data_in => p2_data_in,
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p2_strobe => p2_strobe,
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p2_strobe => p2_strobe,
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p2_data_out => p2_data_out
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p2_data_out => p2_data_out
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);
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);
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end arch;
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end arch;
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